公开(公告)号：US20230141093A1

公开(公告)日：2023-05-11

申请号：US18149130

申请日：2023-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu LIN ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Tzer-Min SHEN ,  Fu-Ting YEN ,  Gary CHAN ,  Keng-Chu LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L21/8234 ,  H01L21/3065

CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L21/823418

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

公开(公告)号：US20230064393A1

公开(公告)日：2023-03-02

申请号：US17461186

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Chung LIN ,  Han-Yu LIN ,  Fang-Wei LEE ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/3065 ,  H01L29/786 ,  H01L29/06

Abstract: The present disclosure describes a method that includes forming a fin structure with a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the second semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening and etching a portion of the second semiconductor layer with a fluorine-containing gas through the opening.

公开(公告)号：US20220319917A1

公开(公告)日：2022-10-06

申请号：US17845891

申请日：2022-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Chang SUN ,  Po-Chin CHANG ,  Akira MINEJI ,  Zi-Wei FANG ,  Pinyen LIN

IPC: H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/535 ,  H01L23/532

Abstract: A method for forming a semiconductor structure includes forming a gate structure on a substrate; depositing a first dielectric layer over the gate structure; depositing a second dielectric layer over the first dielectric layer and having a different density than the first dielectric layer; performing a first etching process on the first and second dielectric layers to form a trench; performing a second etching process on the first and second dielectric layers to modify the trench; filling a conductive material in the modified trench.

公开(公告)号：US20190164820A1

公开(公告)日：2019-05-30

申请号：US15860565

申请日：2018-01-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Chang SUN ,  Po-Chin CHANG ,  Akira MINEJI ,  Zi-Wei FANG ,  Pinyen LIN

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/535 ,  H01L23/532 ,  H01L27/088

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes following steps. A MEOL structure is formed on an etch stop layer. A patterned masking layer with at least one opening is formed on the MEOL structure and a first etching process is performed to form a trench in the MEOL structure. A second etching process is performed to modify at least one sidewall of the trench.

公开(公告)号：US20250089332A1

公开(公告)日：2025-03-13

申请号：US18962707

申请日：2024-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang WU ,  Kuo-An LIU ,  Chan-Lon YANG ,  Bharath Kumar PULICHERLA ,  Li-Te LIN ,  Chung-Cheng WU ,  Gwan-Sin CHANG ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.

公开(公告)号：US20240063288A1

公开(公告)日：2024-02-22

申请号：US18501554

申请日：2023-11-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen LO ,  Jung-Hao CHANG ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/51 ,  H01J37/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/517 ,  H01J37/00 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/67069 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/4966

Abstract: A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

公开(公告)号：US20220384268A1

公开(公告)日：2022-12-01

申请号：US17885410

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chin CHANG ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L23/522 ,  H01L21/3213

Abstract: A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact and a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The conductive via is over the source/drain contact. From a top view, the conductive via has two opposite long sides and two opposite short sides connecting the long sides, and the short sides are shorter than the long sides and more curved than the long sides.

公开(公告)号：US20220359724A1

公开(公告)日：2022-11-10

申请号：US17873962

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen LO ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/033 ,  H01L21/027 ,  H01L29/423 ,  H01L21/308 ,  H01L21/768 ,  H01L29/78 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3213

Abstract: A method includes forming a semiconductor fin on a substrate; forming a dielectric layer over the semiconductor fin; forming a metal gate electrode in the dielectric layer and extending across the semiconductor fin; forming a source/drain regions on the semiconductor fin and on opposite sides of the metal gate electrode; performing a first non-zero bias plasma etching process to the metal gate electrode; after performing the first non-zero bias plasma etching process, performing a first zero bias plasma etching process to the metal gate electrode.

公开(公告)号：US20210359125A1

公开(公告)日：2021-11-18

申请号：US16876466

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Pang-Yen TSAI ,  Keng-Chu LIN ,  Sung-Li WANG ,  Pinyen LIN

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple channel structures suspended over a semiconductor substrate. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the channel structures. The semiconductor device structure further includes a gate stack wrapping around the channel structures. In addition, the semiconductor device structure includes a conductive contact wrapping around terminals of the epitaxial structures.

公开(公告)号：US20200243385A1

公开(公告)日：2020-07-30

申请号：US16260536

申请日：2019-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jui HUANG ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02

Abstract: A method for forming a semiconductor device structure is provided. A gate structure and a source/drain contact structure are formed over a substrate. The gate structure is covered with a capping layer. The capping layer and the source/drain contact structure are successively covered with a first insulating layer and a second insulating layer. A via opening is formed in the second insulating layer to expose the first insulating layer above the source/drain contact structure. The exposed first insulating layer is recessed using a first etching gas mixture including an oxygen gas, to leave a portion of the first insulating layer. The left portion of the first insulating layer using a second etching gas mixture including a hydrogen gas, to expose the source/drain contact structure. A conductive material is formed in the via opening to electrically connect the source/drain contact structure.