公开(公告)号：US20250022763A1

公开(公告)日：2025-01-16

申请号：US18352363

申请日：2023-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Han Tsai ,  Tsung-Yu Chen ,  Hong-Yu Guo ,  Tsung-Shu Lin

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/29 ,  H01L25/10

Abstract: Semiconductor device and methods of manufacture are provided. In an embodiment, the a semiconductor device may include a first semiconductor die; an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite the oxide layer; a first insulating material encapsulating the first semiconductor die and the oxide layer, wherein the first insulating material has a second top surface planar with the first top surface; and a first polymer buffer disposed between a sidewall of the first semiconductor die and a sidewall of the oxide layer, wherein the first polymer buffer has a third top surface planar with both the first top surface and the second top surface.

公开(公告)号：US20240387368A1

公开(公告)日：2024-11-21

申请号：US18788881

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yi Lin ,  Jie Chen ,  Sheng-Han Tsai ,  Yuan Sheng Chiu ,  Chou-Jui Hsu ,  Yu Kuei Yeh ,  Tsung-Shu Lin

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/532

Abstract: A semiconductor device and method of manufacture are presented in which a first pad and a second pad are formed adjacent to each other. A first set of dummy pads is manufactured between the first pad and the second pad and bonding pads are formed in electrical connection to the first pad and the second pad.

公开(公告)号：US20230386908A1

公开(公告)日：2023-11-30

申请号：US17819341

申请日：2022-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Han Tsai ,  Yuan Sheng Chiu ,  Chou-Jui Hsu ,  Tsung-Shu Lin

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76829 ,  H01L21/76807 ,  H01L24/03 ,  H01L2224/03011 ,  H01L2224/02235 ,  H01L2224/02251 ,  H01L2924/35 ,  H01L2224/06179 ,  H01L2224/06151 ,  H01L2224/06155 ,  H01L24/06

Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate, forming a plurality of metal lines and vias in the plurality of dielectric layers, forming a lower portion of an inner seal ring and a lower portion of an outer seal ring extending into the plurality of dielectric layers, depositing a first dielectric layer over the plurality of metal lines and vias, and etching the first dielectric layer to form an opening penetrating through the first dielectric layer. After the first dielectric layer is etched, a top surface of the lower portion of the inner seal ring is exposed, and an entire topmost surface of the lower portion of the outer seal ring is in contact with a bottom surface of the first dielectric layer. An upper portion of the inner seal ring is then formed to extend into the opening and to join the lower portion of the inner seal ring. A second dielectric layer is deposited to cover the upper portion of the inner seal ring.

公开(公告)号：US20250022825A1

公开(公告)日：2025-01-16

申请号：US18510523

申请日：2023-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Han Tsai ,  Tsung-Yu Chen ,  Hong-Yu Guo ,  Tsung-Shu Lin ,  Hsin-Yu Pan

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/58

Abstract: In an embodiment, a method includes: forming active devices over a semiconductor substrate; forming an interconnect structure over the active devices, the interconnect structure comprising a first portion of a seal ring over the semiconductor substrate, the seal ring being electrically insulated from the active devices; forming a first passivation layer over the interconnect structure; forming a first metal pad and a second metal pad extending through the first passivation layer and over the interconnect structure, the first metal pad having a bowl shape, the second metal pad having a step shape; and depositing a second passivation layer over the first metal pad and the second metal pad.

公开(公告)号：US11848270B2

公开(公告)日：2023-12-19

申请号：US16422988

申请日：2019-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Seng Shue ,  Sheng-Han Tsai ,  Kuo-Chin Chang ,  Mirng-Ji Lii ,  Kuo-Ching Hsu

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/023 ,  H01L2224/0224 ,  H01L2224/0225 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02235 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/081 ,  H01L2224/0805 ,  H01L2224/08052 ,  H01L2224/08113 ,  H01L2224/16104

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a redistribution layer over the substrate. The chip structure includes a bonding pad over the redistribution layer. The chip structure includes a shielding pad over the redistribution layer and surrounding the bonding pad. The chip structure includes an insulating layer over the redistribution layer and the shielding pad. The chip structure includes a bump over the bonding pad and the insulating layer. A sidewall of the bump is over the shielding pad.

公开(公告)号：US20230361027A1

公开(公告)日：2023-11-09

申请号：US17819381

申请日：2022-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yi Lin ,  Jie Chen ,  Sheng-Han Tsai ,  Yuan Sheng Chiu ,  Chou-Jui Hsu ,  Yu Kuei Yeh ,  Tsung-Shu Lin

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L23/53209 ,  H01L24/27 ,  H01L24/33 ,  H01L2224/33104

Abstract: A semiconductor device and method of manufacture are presented in which a first pad and a second pad are formed adjacent to each other. A first set of dummy pads is manufactured between the first pad and the second pad and bonding pads are formed in electrical connection to the first pad and the second pad.