公开(公告)号：US20250022763A1

公开(公告)日：2025-01-16

申请号：US18352363

申请日：2023-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Han Tsai ,  Tsung-Yu Chen ,  Hong-Yu Guo ,  Tsung-Shu Lin

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/29 ,  H01L25/10

Abstract: Semiconductor device and methods of manufacture are provided. In an embodiment, the a semiconductor device may include a first semiconductor die; an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite the oxide layer; a first insulating material encapsulating the first semiconductor die and the oxide layer, wherein the first insulating material has a second top surface planar with the first top surface; and a first polymer buffer disposed between a sidewall of the first semiconductor die and a sidewall of the oxide layer, wherein the first polymer buffer has a third top surface planar with both the first top surface and the second top surface.

公开(公告)号：US20250022825A1

公开(公告)日：2025-01-16

申请号：US18510523

申请日：2023-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Han Tsai ,  Tsung-Yu Chen ,  Hong-Yu Guo ,  Tsung-Shu Lin ,  Hsin-Yu Pan

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/58

Abstract: In an embodiment, a method includes: forming active devices over a semiconductor substrate; forming an interconnect structure over the active devices, the interconnect structure comprising a first portion of a seal ring over the semiconductor substrate, the seal ring being electrically insulated from the active devices; forming a first passivation layer over the interconnect structure; forming a first metal pad and a second metal pad extending through the first passivation layer and over the interconnect structure, the first metal pad having a bowl shape, the second metal pad having a step shape; and depositing a second passivation layer over the first metal pad and the second metal pad.

公开(公告)号：US20240234340A1

公开(公告)日：2024-07-11

申请号：US18151545

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Che Chiang ,  Yuan Sheng Chiu ,  Hong-Yu Guo ,  Hsin-Yu Pan ,  Tsung-Shu Lin

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/06517 ,  H01L2224/08147 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2224/9222 ,  H01L2924/0544 ,  H01L2924/05494

Abstract: An integrated circuit package with a perforated stiffener ring and the method of forming the same are provided. The integrated circuit package may comprise an integrated circuit package component having an integrated circuit die on a substrate, an underfill between the integrated circuit package component and the substrate, and a stiffener ring attached to the substrate. The stiffener ring may encircle the integrated circuit package component and the underfill in a top-down view. The stiffener ring may comprise a perforated region, wherein the perforated region may comprise an array of openings extending from a top surface of the stiffener ring to a bottom surface of the stiffener ring.