公开(公告)号：US11848270B2

公开(公告)日：2023-12-19

申请号：US16422988

申请日：2019-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Seng Shue ,  Sheng-Han Tsai ,  Kuo-Chin Chang ,  Mirng-Ji Lii ,  Kuo-Ching Hsu

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/023 ,  H01L2224/0224 ,  H01L2224/0225 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02235 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/081 ,  H01L2224/0805 ,  H01L2224/08052 ,  H01L2224/08113 ,  H01L2224/16104

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a redistribution layer over the substrate. The chip structure includes a bonding pad over the redistribution layer. The chip structure includes a shielding pad over the redistribution layer and surrounding the bonding pad. The chip structure includes an insulating layer over the redistribution layer and the shielding pad. The chip structure includes a bump over the bonding pad and the insulating layer. A sidewall of the bump is over the shielding pad.

公开(公告)号：US11244919B2

公开(公告)日：2022-02-08

申请号：US16367273

申请日：2019-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wen Hsiao ,  Chen-Shien Chen ,  Kuo-Ching Hsu ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A package structure is provided comprising a die, a redistribution layer, at least one integrated passive device (IPD), a plurality of solder balls and a molding compound. The die comprises a substrate and a plurality of conductive pads. The redistribution layer is disposed on the die, wherein the redistribution layer comprises first connection structures and second connection structures. The IPD is disposed on the redistribution layer, wherein the IPD is connected to the first connection structures of the redistribution layer. The plurality of solder balls is disposed on the redistribution layer, wherein the solder balls are disposed and connected to the second connection structures of the redistribution layer. The molding compound is disposed on the redistribution layer, and partially encapsulating the IPD and the plurality of solder balls, wherein top portions of the solder balls and a top surface of the IPD are exposed from the molding compound.

公开(公告)号：US20180151524A1

公开(公告)日：2018-05-31

申请号：US15452674

申请日：2017-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wen Hsiao ,  Chen-Shien Chen ,  Kuo-Ching Hsu ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L21/78

CPC classification number: H01L24/08 ,  H01L21/561 ,  H01L23/3114 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/08265 ,  H01L2224/1191 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/14134 ,  H01L2224/14135 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2924/19103 ,  H01L2924/00012

Abstract: A package structure is provided comprising a die, a redistribution layer, at least one integrated passive device (IPD), a plurality of solder balls and a molding compound. The die comprises a substrate and a plurality of conductive pads. The redistribution layer is disposed on the die, wherein the redistribution layer comprises first connection structures and second connection structures. The IPD is disposed on the redistribution layer, wherein the IPD is connected to the first connection structures of the redistribution layer. The plurality of solder balls is disposed on the redistribution layer, wherein the solder balls are disposed and connected to the second connection structures of the redistribution layer. The molding compound is disposed on the redistribution layer, and partially encapsulating the IPD and the plurality of solder balls, wherein top portions of the solder balls and a top surface of the IPD are exposed from the molding compound.

公开(公告)号：US20240321661A1

公开(公告)日：2024-09-26

申请号：US18679091

申请日：2024-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Kuo-Ching Hsu ,  Wei-Hung Lin ,  Hui-Min Huang ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L23/5384 ,  H01L24/81

Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.

公开(公告)号：US11842935B2

公开(公告)日：2023-12-12

申请号：US17318703

申请日：2021-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Kuo-Ching Hsu ,  Wei-Hung Lin ,  Hui-Min Huang ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L23/5384 ,  H01L24/81

Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.

公开(公告)号：US20240266304A1

公开(公告)日：2024-08-08

申请号：US18637539

申请日：2024-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao Chun Liu ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/585 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/35121

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.

公开(公告)号：US20220262694A1

公开(公告)日：2022-08-18

申请号：US17318703

申请日：2021-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Kuo-Ching Hsu ,  Wei-Hung Lin ,  Hui-Min Huang ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538

Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.

公开(公告)号：US11335634B2

公开(公告)日：2022-05-17

申请号：US16893467

申请日：2020-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Huan Chen ,  Kuo-Ching Hsu ,  Chen-Shien Chen

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A method for forming a chip package structure is provided. The method includes providing a wiring substrate. The method includes sequentially forming a nickel-containing layer and a gold-containing layer over the first pad. The method includes forming a conductive protection layer covering the gold-containing layer over the nickel-containing layer. The method includes bonding a chip to the wiring substrate through a conductive bump and a flux layer surrounding the conductive bump. The conductive bump is between the second pad and the chip. The method includes removing the flux layer while the conductive protection layer covers the nickel-containing layer.

公开(公告)号：US11302537B2

公开(公告)日：2022-04-12

申请号：US16837381

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ching Hsu ,  Yu-Huan Chen ,  Chen-Shien Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: A method for forming a chip package structure is provided. The method includes providing a wiring substrate including a substrate, a pad, and a polymer layer. The polymer layer is over the substrate and the pad, and the polymer layer has a first opening exposing the pad. The method includes forming a conductive adhesive layer over the polymer layer and the pad. The conductive adhesive layer is in direct contact with and conformally covers the polymer layer and the pad. The method includes forming a nickel layer over the conductive adhesive layer. The nickel layer is thicker than the conductive adhesive layer, and the nickel layer and the conductive adhesive layer are made of different materials. The method includes bonding a chip to the wiring substrate through a conductive bump. The conductive bump is between the nickel layer and the chip.

公开(公告)号：US20240379584A1

公开(公告)日：2024-11-14

申请号：US18780104

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Tseng ,  Yu-Feng Chen ,  Cheng Jen Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Kuo-Ching Hsu ,  Hong-Seng Shue ,  Ming-Hong Cha ,  Chao-Yi Wang ,  Mirng-Ji Lii

IPC: H01L23/58 ,  H01L21/02 ,  H01L21/48 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.