公开(公告)号：US20250060660A1

公开(公告)日：2025-02-20

申请号：US18403574

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yeh LEE ,  Ching-Fang YU ,  Hsueh-Wei HUANG ,  Yen-Cheng HO ,  Wei-Cheng LIN ,  Hsin-Yi YIN

IPC: G03F1/42

Abstract: A method includes: generating a designed mask overlay mark associated with an actual mask overlay mark to be formed in a mask; forming the actual mask overlay mark in the mask based on the designed mask overlay mark, the actual mask overlay mark including a plurality of overlay patterns; forming a device feature pattern adjacent to the actual mask overlay mark; forming an alignment of the mask by a mask metrology apparatus including a light source having a wavelength and a numerical aperture, wherein a pitch between adjacent two of the plurality of overlay patterns does not exceed the wavelength divided by twice the numerical aperture; and forming a pattern in a layer of a wafer by transferring the device feature pattern while the mask is under the alignment.

公开(公告)号：US20210183772A1

公开(公告)日：2021-06-17

申请号：US17164449

申请日：2021-02-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng LIN ,  Cheng-Chi CHUANG ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Hui-Ting YANG ,  Wayne LAI

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/02 ,  H01L27/088 ,  H01L27/118

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.

公开(公告)号：US20180166431A1

公开(公告)日：2018-06-14

申请号：US15699990

申请日：2017-09-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Cheng LIN ,  Hui-Ting YANG ,  Shih-Wei PENG ,  Jiann-Tyng TZENG ,  Charles Chew-Yuen YOUNG ,  Chih-Ming LAI

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/088 ,  H01L27/0886

Abstract: A semiconductor device includes at least one first gate strip, at least one second gate strip, at least one first conductive line and at least one first conductive via. An end surface of the at least one first gate strip and an end surface of the at least one second gate strip are opposite each other. The at least one first conductive line is over the at least one first gate strip and the at least one second gate strip and across the end surface of the at least one first gate strip and the end surface of the at least one second gate strip. The at least one first conductive via connects the at least one first conductive line and the at least one first gate strip.

公开(公告)号：US20240178139A1

公开(公告)日：2024-05-30

申请号：US18437130

申请日：2024-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-An LAI ,  Shih-Wei PENG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L23/528 ,  G06F30/31 ,  G06F30/394 ,  G06F30/398 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L23/528 ,  G06F30/394 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696 ,  G06F30/31 ,  G06F30/398

Abstract: Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.

公开(公告)号：US20220359512A1

公开(公告)日：2022-11-10

申请号：US17875060

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei PENG ,  Hui-Zhong ZHUANG ,  Jiann-Tyng TZENG ,  Li-Chun TIEN ,  Pin-Dai SUE ,  Wei-Cheng LIN

IPC: H01L27/092 ,  H03K17/687

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

公开(公告)号：US20240395623A1

公开(公告)日：2024-11-28

申请号：US18790968

申请日：2024-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Wei PENG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L21/8234 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: A device includes first and second transistors, a conductive contact, a dielectric layer, and a conductive via. The first transistor includes a first gate, a first source/drain and a second source/drain at opposite sides of the first gate. The second transistor includes a second gate, a third source/drain and a fourth source/drain at opposite sides of the second gate. The conductive contact extends across the first source/drain and the third source/drain along a longitudinal direction of the first gate. The dielectric layer spaces apart the conductive contact from the first source/drain. The conductive via is in contact with the conductive contact. The conductive via vertically overlaps with the conductive contact and the dielectric layer.

公开(公告)号：US20240387369A1

公开(公告)日：2024-11-21

申请号：US18789467

申请日：2024-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hung SHEN ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Wei-Cheng LIN

IPC: H01L23/528 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes: disposing a first conductive segment; disposing a first conductive via above the first conductive segment; disposing a first conductive line above the first conductive via; and disposing a second conductive segment electrically coupled to the first conductive line through a third conductive segment, the first conductive segment, and the first conductive via.

公开(公告)号：US20220020738A1

公开(公告)日：2022-01-20

申请号：US16933570

申请日：2020-07-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-An LAI ,  Shih-Wei PENG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L27/02 ,  H03K19/17736 ,  H01L23/522 ,  H01L21/8238

Abstract: An integrated circuit includes a semiconductor substrate, transistors on the semiconductor, horizontal routing tracks extending in a first direction in a first metal layer, and one or more backside routing tracks extending in the first direction in a backside metal layer. Each transistor has a gate terminal, a source terminal, and a drain terminal. A first transistor has a first terminal, a second terminal, and a third terminal. A first horizontal routing track of the horizontal routing tracks is conductively connected to the first terminal of the first transistor through a via connector. A first backside routing track is conductively connected to the second terminal of the first transistor through a backside via connector. The backside metal layer and the first metal layer are formed at opposite sides of the semiconductor substrate.

公开(公告)号：US20210265217A1

公开(公告)日：2021-08-26

申请号：US16800834

申请日：2020-02-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Wei PENG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

Abstract: A device includes a first transistor, a second transistor, and a contact. The first transistor includes a first source/drain, a second source/drain, and a first gate between the first and second source/drains. The second transistor includes a third source/drain, a fourth source/drain, and a second gate between the third and fourth source/drains. The contact covers the first source/drain of the first transistor and the third source/drain of the third transistor. The first contact is electrically connected to the first source/drain of the first transistor and electrically isolated from the third source/drain of the third transistor.

公开(公告)号：US20210118805A1

公开(公告)日：2021-04-22

申请号：US16656715

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou SIO ,  Cheng-Chi CHUANG ,  Chia-Tien WU ,  Jiann-Tyng TZENG ,  Shih-Wei PENG ,  Wei-Cheng LIN

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the third interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.