公开(公告)号：US11968828B2

公开(公告)日：2024-04-23

申请号：US16506823

申请日：2019-07-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/788 ,  H10B41/30 ,  H10B41/40 ,  H10B41/42

CPC classification number: H10B41/42 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/40114 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30 ,  H10B41/40

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a first gate stack. An isolation feature is formed in the semiconductor substrate, and a cell region and a peripheral region adjacent to the cell region are defined in the semiconductor substrate. The first gate stack is disposed on the peripheral region of the semiconductor substrate. The first gate stack includes a first dielectric layer and a gate electrode layer disposed on the first dielectric layer and covering a top surface of the first dielectric layer. The first dielectric layer is disposed on the semiconductor substrate and has a concave profile.

公开(公告)号：US11942475B2

公开(公告)日：2024-03-26

申请号：US16657396

申请日：2019-10-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28052 ,  H01L21/823431 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.

公开(公告)号：US11869888B2

公开(公告)日：2024-01-09

申请号：US17870415

申请日：2022-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823418 ,  H01L21/823437

Abstract: The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.

公开(公告)号：US11637113B2

公开(公告)日：2023-04-25

申请号：US17226348

申请日：2021-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： ShihKuang Yang ,  Yong-Shiuan Tsair ,  Po-Wei Liu ,  Hung-Ling Shih ,  Yu-Ling Hsu ,  Chieh-Fei Chiu ,  Wen-Tuo Huang

IPC: H01L29/788 ,  H01L27/11521 ,  H01L29/423 ,  H01L21/28 ,  H01L29/78

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°

公开(公告)号：US20210183875A1

公开(公告)日：2021-06-17

申请号：US17190678

申请日：2021-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Tuo Huang ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin ,  Shih Kuang Yang

IPC: H01L27/11521 ,  H01L23/528 ,  H01L23/532 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L21/768 ,  H01L23/522 ,  H01L29/788 ,  H01L21/28

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

公开(公告)号：US20200105346A1

公开(公告)日：2020-04-02

申请号：US16400361

申请日：2019-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Kuang Yang ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin

IPC: G11C16/08 ,  G11C11/16 ,  H01L27/108

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

公开(公告)号：US12148752B2

公开(公告)日：2024-11-19

申请号：US17815180

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.

公开(公告)号：US11004858B2

公开(公告)日：2021-05-11

申请号：US16370736

申请日：2019-03-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsun-Kai Tsao ,  Hung-Ling Shih ,  Po-Wei Liu ,  Shun-Shing Yang ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair ,  S. K. Yang

IPC: H01L27/11529 ,  H01L21/28 ,  H01L29/423 ,  H01L27/11521 ,  H01L21/3105

Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

公开(公告)号：US10978463B2

公开(公告)日：2021-04-13

申请号：US16748584

申请日：2020-01-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： ShihKuang Yang ,  Yong-Shiuan Tsair ,  Po-Wei Liu ,  Hung-Ling Shih ,  Yu-Ling Hsu ,  Chieh-Fei Chiu ,  Wen-Tuo Huang

IPC: H01L27/115 ,  H01L27/11521 ,  H01L29/423 ,  H01L21/28 ,  H01L29/78

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°

公开(公告)号：US10541245B2

公开(公告)日：2020-01-21

申请号：US16204840

申请日：2018-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： ShihKuang Yang ,  Yong-Shiuan Tsair ,  Po-Wei Liu ,  Hung-Ling Shih ,  Yu-Ling Hsu ,  Chieh-Fei Chiu ,  Wen-Tuo Huang

IPC: H01L29/788 ,  H01L27/11521 ,  H01L29/423 ,  H01L21/28 ,  H01L29/78

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°