公开(公告)号：US12094771B2

公开(公告)日：2024-09-17

申请号：US17883986

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Jiun Lin ,  Yu Chao Lin ,  Tung Ying Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66

CPC classification number: H01L21/76843 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76874 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L29/66795

Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

公开(公告)号：US11925127B2

公开(公告)日：2024-03-05

申请号：US17812773

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Yu Chao Lin ,  Shao-Ming Yu

IPC: H10N70/00

CPC classification number: H10N70/063 ,  H10N70/021 ,  H10N70/841 ,  H10N70/8828

Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.

公开(公告)号：US20220352465A1

公开(公告)日：2022-11-03

申请号：US17867460

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Shao-Ming Yu ,  Yu Chao Lin

IPC: H01L45/00 ,  H01L27/24

Abstract: In an embodiment, a device includes: a first metallization layer over a substrate, the substrate including active devices; a first bit line over the first metallization layer, the first bit line connected to first interconnects of the first metallization layer, the first bit line extending in a first direction, the first direction parallel to gates of the active devices; a first phase-change random access memory (PCRAM) cell over the first bit line; a word line over the first PCRAM cell, the word line extending in a second direction, the second direction perpendicular to the gates of the active devices; and a second metallization layer over the word line, the word line connected to second interconnects of the second metallization layer.

公开(公告)号：US20220352464A1

公开(公告)日：2022-11-03

申请号：US17812773

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Yu Chao Lin ,  Shao-Ming Yu

IPC: H01L45/00

Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.

公开(公告)号：US11411180B2

公开(公告)日：2022-08-09

申请号：US16992210

申请日：2020-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Yu Chao Lin ,  Shao-Ming Yu

IPC: H01L45/00

Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.

公开(公告)号：US10748768B2

公开(公告)日：2020-08-18

申请号：US16217167

申请日：2018-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chao Lin ,  Chao-Cheng Chen ,  Chun-Hung Lee ,  Yu-Lung Yang

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3065 ,  H01L21/02

Abstract: A method includes forming mandrel patterns over a substrate; depositing a spacer layer over the mandrel patterns and onto sidewalls of the mandrel patterns; trimming the spacer layer to reduce a thickness of the spacer layer along a pattern width direction; and etching the spacer layer to expose the mandrel patterns, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. The trimming of the spacer layer and the etching of the spacer layer are performed in separate processes. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns.

公开(公告)号：US10541365B1

公开(公告)日：2020-01-21

申请号：US15998689

申请日：2018-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chao Lin ,  Jau-Yi Wu ,  Yu-Sheng Chen ,  Carlos H. Diaz

IPC: H01L45/00 ,  H01L27/24

Abstract: The current disclosure describes techniques for patterning a phase-change memory layer. A SiON layer is used as a first hard mask and an electrical conductive protective layer is used as a second hard mask to pattern the phase-change memory layer. An organic BARC layer is sued to improve the photolithography accuracy. The thickness ratio between the organic BARC layer and the hard mask SiON layer and the etching conditions of the hard mask SiON layer are controlled such that the patterned organic BARC layer is completely or near completely resolved simultaneously with the patterning of the hard mask SiON layer.

公开(公告)号：US20240363402A1

公开(公告)日：2024-10-31

申请号：US18769054

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Jiun Lin ,  Yu Chao Lin ,  Tung Ying Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66

CPC classification number: H01L21/76843 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76874 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L29/66795

Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

公开(公告)号：US11588106B2

公开(公告)日：2023-02-21

申请号：US17081159

申请日：2020-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chao Lin ,  Jui-Ming Chen ,  Shao-Ming Yu ,  Tung Ying Lee ,  Yu-Sheng Chen

IPC: H01L45/00 ,  H01L27/24

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip that includes depositing a phase change material layer over a bottom electrode. The phase change material is configured to change its degree of crystallinity upon temperature changes. A top electrode layer is deposited over the phase change material layer, and a hard mask layer is deposited over the top electrode layer. The top electrode layer and the hard mask layer are patterned to remove outer portions of the top electrode layer and to expose outer portions of the phase change material layer. An isotropic etch is performed to remove portions of the phase change material layer that are uncovered by the top electrode layer and the hard mask layer. The isotropic etch removes the portions of the phase change material layer faster than portions of the top electrode layer and the hard mask layer.

公开(公告)号：US11450563B2

公开(公告)日：2022-09-20

申请号：US17039390

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Jiun Lin ,  Yu Chao Lin ,  Tung Ying Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.