公开(公告)号：US20170194147A1

公开(公告)日：2017-07-06

申请号：US15096541

申请日：2016-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chao Lin ,  Chao-Cheng Chen ,  Chun-Hung Lee ,  Yu-Lung Yang

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/30655 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139

Abstract: An integrated circuit manufacturing method includes forming mandrel patterns over a patterning layer of a substrate; and forming a spacer layer over the patterning layer, over the mandrel patterns, and onto sidewalls of the mandrel patterns. The method further includes trimming the spacer layer using a dry etching technique such that a space between adjacent sidewalls of the spacer layer substantially matches a dimension of the mandrel patterns along a pattern width direction. The method further includes etching the spacer layer to expose the mandrel patterns and the patterning layer, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns. The method further includes transferring a pattern of the patterned spacer layer to the patterning layer.

公开(公告)号：US10748768B2

公开(公告)日：2020-08-18

申请号：US16217167

申请日：2018-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chao Lin ,  Chao-Cheng Chen ,  Chun-Hung Lee ,  Yu-Lung Yang

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3065 ,  H01L21/02

Abstract: A method includes forming mandrel patterns over a substrate; depositing a spacer layer over the mandrel patterns and onto sidewalls of the mandrel patterns; trimming the spacer layer to reduce a thickness of the spacer layer along a pattern width direction; and etching the spacer layer to expose the mandrel patterns, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. The trimming of the spacer layer and the etching of the spacer layer are performed in separate processes. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns.

公开(公告)号：US11948810B2

公开(公告)日：2024-04-02

申请号：US15906689

申请日：2018-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Chao Yin ,  Yuling Chiu ,  Yu-Lung Yang ,  Hung-Bin Lin

IPC: H01L21/67

CPC classification number: H01L21/67017 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/6719 ,  H01L21/67196 ,  H01L21/67126 ,  H01L21/67201

Abstract: A vacuum apparatus includes process chambers, and a transfer chamber coupled to the process chambers. The transfer chamber includes one or more vacuum ports, thorough which a gas inside the transfer chamber is exhausted, and vent ports, from which a vent gas is supplied. The one or more vacuum ports and the vent ports are arranged such that air flows from at least one of the vent ports to the one or more vacuum ports are line-symmetric with respect to a center line of the transfer chamber.

公开(公告)号：US20190122888A1

公开(公告)日：2019-04-25

申请号：US16217167

申请日：2018-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chao Lin ,  Chao-Cheng Chen ,  Chun-Hung Lee ,  Yu-Lung Yang

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/311

Abstract: A method includes forming mandrel patterns over a substrate; depositing a spacer layer over the mandrel patterns and onto sidewalls of the mandrel patterns; trimming the spacer layer to reduce a thickness of the spacer layer along a pattern width direction; and etching the spacer layer to expose the mandrel patterns, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. The trimming of the spacer layer and the etching of the spacer layer are performed in separate processes. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns.

公开(公告)号：US10157742B2

公开(公告)日：2018-12-18

申请号：US15096541

申请日：2016-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chao Lin ,  Chao-Cheng Chen ,  Chun-Hung Lee ,  Yu-Lung Yang

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3065 ,  H01L21/02

Abstract: An integrated circuit manufacturing method includes forming mandrel patterns over a patterning layer of a substrate; and forming a spacer layer over the patterning layer, over the mandrel patterns, and onto sidewalls of the mandrel patterns. The method further includes trimming the spacer layer using a dry etching technique such that a space between adjacent sidewalls of the spacer layer substantially matches a dimension of the mandrel patterns along a pattern width direction. The method further includes etching the spacer layer to expose the mandrel patterns and the patterning layer, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns. The method further includes transferring a pattern of the patterned spacer layer to the patterning layer.