公开(公告)号：US5885857A

公开(公告)日：1999-03-23

申请号：US7619

申请日：1998-01-15

申请人： Takahisa Yamaha ,  Yushi Inoue ,  Masaru Naito

发明人： Takahisa Yamaha ,  Yushi Inoue ,  Masaru Naito

IPC分类号： H01L23/52 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L21/283 ,  H01L21/306 ,  H01L21/311

CPC分类号： H01L23/3171 ,  H01L2924/0002

摘要： A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.

摘要翻译： 一种树脂模制半导体器件，其具有布线层和包括SOG膜的层间绝缘层，能够抑制由于热应力引起的SOG膜中的裂纹的产生。 在半导体芯片的外周区域中，在包括SOG膜的层间绝缘层中形成通孔，以显着减少残留的SOG膜。 作为包含SOG膜的层间绝缘层的下层，形成虚拟布线图案，以使虚拟布线图案上的SOG膜变薄。 也可以通过使用较高级布线层，埋入通孔并接触下层虚拟布线图案来形成虚拟布线图案。

公开(公告)号：US5763936A

公开(公告)日：1998-06-09

申请号：US637227

申请日：1996-04-24

申请人： Takahisa Yamaha ,  Yushi Inoue ,  Masaru Naito

发明人： Takahisa Yamaha ,  Yushi Inoue ,  Masaru Naito

IPC分类号： H01L23/52 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/58 ,  H01L23/48 ,  H01L23/544

CPC分类号： H01L23/3171 ,  H01L2924/0002

摘要： A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.

摘要翻译： 一种树脂模制半导体器件，其具有布线层和包括SOG膜的层间绝缘层，能够抑制由于热应力引起的SOG膜中的裂纹的产生。 在半导体芯片的外周区域中，在包括SOG膜的层间绝缘层中形成通孔，以显着减少残留的SOG膜。 作为包含SOG膜的层间绝缘层的下层，形成虚拟布线图案，以使虚拟布线图案上的SOG膜变薄。 也可以通过使用较高级布线层，埋入通孔并接触下层虚拟布线图案来形成虚拟布线图案。

公开(公告)号：US06251805B1

公开(公告)日：2001-06-26

申请号：US08993681

申请日：1997-12-18

申请人： Takahisa Yamaha ,  Yushi Inoue

发明人： Takahisa Yamaha ,  Yushi Inoue

IPC分类号： H01L2131

CPC分类号： H01L21/02164 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/31051 ,  H01L21/3124 ,  H01L21/316

摘要： A hydrogen silsesquloxane resin film is formed flat by spin-coating or another such method on the surface of a semiconductor substrate or another such treatment wafer 38, after which the above-mentioned resin film is subjected to a heat treatment in an inert gas atmosphere to form a silicon oxide film of preceramic phase. In a hot plate type of heating apparatus, the wafer 38 is placed on a conveyor belt 34 and moved above a heat-generating block 30, which heats the wafer in the open air and converts the preceramic-phase silicon oxide film into a ceramic-phase silicon oxide film. The silane generated during heating does not adhere to the wafer surface as SiO2 particles, so no microscopic protrusions are produced. N2 or another such inert gas may be blown at the wafer 38 during heating.

摘要翻译： 在半导体基板或另一个这样的处理晶片38的表面上，通过旋涂或其他这种方法将氢硅倍半酚树脂膜平坦地形成，之后将上述树脂膜在惰性气体气氛中进行热处理 形成前陶瓷相的氧化硅膜。 在热板式加热装置中，将晶片38放置在输送带34上并移动到发热块30上方，该发热块30在露天加热晶片，并将陶瓷前氧化硅膜转换为陶瓷 - 相氧化硅膜。 在加热过程中产生的硅烷作为SiO 2颗粒不粘附到晶片表面，因此不产生微观突起。 在加热期间，可以在晶片38上吹入N 2或另一种这样的惰性气体。

公开(公告)号：US5750403A

公开(公告)日：1998-05-12

申请号：US678568

申请日：1996-07-12

申请人： Yushi Inoue ,  Takahisa Yamaha

发明人： Yushi Inoue ,  Takahisa Yamaha

IPC分类号： H01L21/3205 ,  C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  B05D3/02

CPC分类号： C23C16/401 ,  H01L21/316 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76828

摘要： On a first insulating film covering a substrate, wiring layer patterns are formed and thereafter, a second insulating film of plasma CVD--SiO.sub.2 or the like is formed thereon. A hydrogen silsesquioxane resin film having a flat surface is spin-coated on the second insulating film. Thereafter, the resin film is subjected to a first heat treatment in an inert gas atmosphere to convert the resin film into a silicon oxide film of a preceramic phase. On this silicon oxide film, a third insulating film of plasma CVD--SiO.sub.2 or the like is formed. Thereafter, a second heat treatment is performed to convert the silicon oxide film of preceramic phase into a silicon oxide film of a ceramic phase, while preventing fine size projections from being formed on the surface of the silicon oxide film. Thereafter, a second wiring layer is formed on the third insulating film. It is possible to planarize an interlevel insulating film and improve a process yield.

摘要翻译： 在覆盖基板的第一绝缘膜上形成布线层图案，之后在其上形成等离子体CVD-SiO 2等的第二绝缘膜。 将具有平坦表面的氢倍半硅氧烷树脂膜旋涂在第二绝缘膜上。 然后，在惰性气体气氛中对树脂膜进行第一次热处理，将树脂膜转换成陶瓷相的氧化硅膜。 在该氧化硅膜上形成等离子体CVD-SiO 2等的第三绝缘膜。 此后，进行第二次热处理，将陶瓷相的氧化硅膜转化为陶瓷相的氧化硅膜，同时防止在氧化硅膜的表面上形成微小的突起。 此后，在第三绝缘膜上形成第二布线层。 可以平坦化层间绝缘膜并提高工艺成品率。

公开(公告)号：US5904576A

公开(公告)日：1999-05-18

申请号：US961276

申请日：1997-10-30

申请人： Takahisa Yamaha ,  Yushi Inoue

发明人： Takahisa Yamaha ,  Yushi Inoue

IPC分类号： H01L21/3205 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/31

CPC分类号： H01L21/76801 ,  H01L21/316 ,  H01L21/76804 ,  H01L21/76826 ,  H01L21/76828

摘要： After wiring patterns are formed on an insulating film covering the surface of a substrate, an insulating film such as plasma CVD SiO.sub.2 is formed covering the wiring patterns. A hydrogen silsesquioxane resin film with a flat surface is formed by spin coating or the like on the insulating film. Thereafter, the resin film is changed into a pre-ceramic silicon oxide film by performing heat treatment in an inert gas atmosphere. On this pre-ceramic silicon oxide film, an insulating film such as plasma enhanced CVD SiO.sub.2 film is formed and another wiring layer is formed on the insulating film. This method of forming a multi-layer wiring structure allows an interlayer insulating film to be planarized, and improves a yield of wiring formation.

摘要翻译： 在覆盖基板的表面的绝缘膜上形成布线图案之后，形成覆盖布线图案的等离子体CVD SiO 2等绝缘膜。 通过在绝缘膜上旋涂等形成具有平坦表面的氢倍半硅氧烷树脂薄膜。 此后，通过在惰性气体气氛中进行热处理将树脂膜变成预陶瓷氧化硅膜。 在该预陶瓷氧化硅膜上形成等离子体增强CVD SiO 2膜等绝缘膜，在绝缘膜上形成另一配线层。 这种形成多层布线结构的方法允许层间绝缘膜平坦化，并且提高布线形成的产量。

公开(公告)号：US5821162A

公开(公告)日：1998-10-13

申请号：US679738

申请日：1996-07-12

申请人： Takahisa Yamaha ,  Yushi Inoue

发明人： Takahisa Yamaha ,  Yushi Inoue

IPC分类号： H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/538 ,  H01L21/4763

CPC分类号： H01L21/76801 ,  H01L21/316 ,  H01L21/76828

摘要： On a first insulating film covering a substrate, wiring layer patterns are formed. Thereafter, a second insulating film of plasma CVD--SiO.sub.2 or the like is formed thereon. A hydrogen silsesquioxane resin film having a flat surface is spin-coated on the second insulating film. Thereafter, the resin film is subjected to a first heat treatment in an inert gas atmosphere to convert the resin film into a silicon oxide film of a preceramic phase. This preceramic silicon oxide film is subjected to a second heat treatment in an oxidizing atmosphere to convert this preceramic silicon oxide film into a silicon oxide film of a ceramic phase. In this case, a fine size projection is generated on the surface of the ceramic silicon oxide film. On the ceramic silicon oxide film, a third insulating film of plasma CVD--PSG or the like is formed which does not reflect the fine size projection. Thereafter, a fourth insulating film of plasma CVD--SiO.sub.2 is formed, followed by formation of a second wiring layer. It is possible to planarize an interlevel insulating film and improve a process yield.

摘要翻译： 在覆盖基板的第一绝缘膜上形成布线层图案。 此后，在其上形成等离子体CVD-SiO 2等的第二绝缘膜。 将具有平坦表面的氢倍半硅氧烷树脂膜旋涂在第二绝缘膜上。 然后，在惰性气体气氛中对树脂膜进行第一次热处理，将树脂膜转换成陶瓷相的氧化硅膜。 该氧化硅陶瓷氧化膜在氧化气氛中进行第二次热处理，将该陶瓷氧化硅膜转化为陶瓷相的氧化硅膜。 在这种情况下，在陶瓷氧化硅膜的表面上产生细小的投射。 在陶瓷氧化硅膜上形成等离子体CVD-PSG等的第三绝缘膜，其不反映微细尺寸的投影。 此后，形成等离子体CVD-SiO 2的第四绝缘膜，然后形成第二布线层。 可以平坦化层间绝缘膜并提高工艺成品率。

公开(公告)号：US20060105541A1

公开(公告)日：2006-05-18

申请号：US11272668

申请日：2005-11-15

申请人： Yushi Inoue

发明人： Yushi Inoue

IPC分类号： H01L21/76

CPC分类号： H01L21/76235

摘要： A trench isolation method for semiconductor devices, the method includes the steps of: successively depositing a pad oxide film and a nitride film on a semiconductor substrate and then selectively removing the pad oxide film and the nitride film to form a mask pattern; forming trench regions in the semiconductor substrate using the formed mask pattern; depositing a thermal oxide film on side walls and bottoms of the formed trench regions by thermal oxidation; depositing on the semiconductor substrate having the trench regions a first buried oxide film having such a thickness that the trench regions are not completely filled by thermal CVD using SiH4/N2O gas; depositing a plasma oxide film as a second buried oxide film, by HDP plasma CVD, such that the trench regions are filled with the film; and removing upper portions of the first and second buried oxide films by CMP (chemical mechanical polishing) using the nitride film as a stopper and then etching away the nitride film and the pad oxide film, wherein the gas flow-rate ratio of SiH4/N2O is set to such a ratio that formation of fine foreign substances in the first buried oxide film can be suppressed in the step of depositing the first buried oxide film.

摘要翻译： 一种半导体器件的沟槽隔离方法，该方法包括以下步骤：在半导体衬底上依次沉积衬垫氧化物膜和氮化物膜，然后选择性地去除衬底氧化物膜和氮化物膜以形成掩模图案; 使用所形成的掩模图案在半导体衬底中形成沟槽区域; 通过热氧化在形成的沟槽区域的侧壁和底部上沉积热氧化膜; 在具有沟槽区域的半导体衬底上沉积第一掩埋氧化物膜，该第一掩埋氧化物膜具有这样的厚度，即使用SiH 4 / N 2 O 2，通过热CVD不完全填充沟槽区域 加油站; 通过HDP等离子体CVD沉积作为第二掩埋氧化物膜的等离子体氧化物膜，使得沟槽区域被膜填充; 并通过CMP（化学机械抛光），使用氮化物膜作为阻挡层去除第一和第二掩埋氧化物膜的上部，然后蚀刻掉氮化物膜和衬垫氧化膜，其中SiH 4 2 O设定为在沉积第一掩埋氧化膜的步骤中能够抑制在第一掩埋氧化膜中形成细小异物的比例。

公开(公告)号：US06503849B1

公开(公告)日：2003-01-07

申请号：US09680951

申请日：2000-10-10

申请人： Yoshihiro Ooishi ,  Yushi Inoue

发明人： Yoshihiro Ooishi ,  Yushi Inoue

IPC分类号： H01L2102

CPC分类号： H01L21/76802 ,  C23C18/1208 ,  C23C18/1279 ,  H01L21/316 ,  H01L21/76801

摘要： A method for forming an insulating film, wherein a precursor film of a coating type insulating film having Si—H bonding is coated, the precursor film is calcined in an atmosphere containing at least one of an inert gas and oxygen gas for converting it into a ceramic film as the insulating film, and then the ceramic film is cooled under reduced pressure lower than that for the calcination.

摘要翻译： 一种形成绝缘膜的方法，其中涂覆具有Si-H键的涂层型绝缘膜的前体膜，所述前体膜在包含惰性气体和氧气中的至少一种的气氛中煅烧，以将其转化为 陶瓷膜作为绝缘膜，然后将陶瓷膜在低于煅烧时的减压下冷却。

公开(公告)号：US5976966A

公开(公告)日：1999-11-02

申请号：US964580

申请日：1997-11-05

申请人： Yushi Inoue

发明人： Yushi Inoue

IPC分类号： H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763

CPC分类号： H01L21/02164 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3124 ,  H01L21/316 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76814

摘要： An insulating film is formed by CVD on the surface of a semiconductor substrate formed with circuit elements such as transistors, and thereafter a hydrogen silsesquioxane resin film is formed on the insulating film by spin-coating or the like. This resin film is sequentially subjected to low temperature annealing at 400.degree. C. or lower and then to high temperature annealing at 700.degree. C. or higher. The low temperature annealing changes the resin film into a silicon oxide film, and the high temperature annealing is performed in order to make dense the film quality of the silicon oxide film. The high temperature annealing is performed by rapid thermal annealing in an oxidizing atmosphere of water vapor or the like. A CVD insulating film is formed on the densified silicon oxide film and planarized by CMP or the like, according to necessity. A contact hole is formed through the CVD insulating film, densified silicon oxide film and the insulating film, and a wiring layer is thereafter deposited.

摘要翻译： 在由诸如晶体管的电路元件形成的半导体衬底的表面上通过CVD形成绝缘膜，然后通过旋涂等在绝缘膜上形成氢倍半硅氧烷树脂膜。 该树脂膜依次在400℃以下进行低温退火，然后在700℃以上进行高温退火。 低温退火将树脂膜变更为氧化硅膜，进行高温退火以使氧化硅膜的膜质量密集。 高温退火通过在水蒸气等的氧化气氛中快速热退火进行。 根据需要，在致密化的氧化硅膜上形成CVD绝缘膜，并通过CMP等进行平坦化。 通过CVD绝缘膜，致密氧化硅膜和绝缘膜形成接触孔，然后沉积布线层。

公开(公告)号：US08530877B2

公开(公告)日：2013-09-10

申请号：US13182696

申请日：2011-07-14

申请人： Junya Onishi ,  Shinobu Yamazaki ,  Kazuya Ishihara ,  Yushi Inoue ,  Yukio Tamai ,  Nobuyoshi Awaya

发明人： Junya Onishi ,  Shinobu Yamazaki ,  Kazuya Ishihara ,  Yushi Inoue ,  Yukio Tamai ,  Nobuyoshi Awaya

IPC分类号： H01L47/00

CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146

摘要： A variable resistance element that can stably perform a switching operation with a property variation being reduced by suppressing a sharp current that accompanies completion of forming process, and a non-volatile semiconductor memory device including the variable resistance element are realized. The non-volatile semiconductor memory device uses the variable resistance element for storing information in which a resistance changing layer is interposed between a first electrode and a second electrode, and a buffer layer is inserted between the first electrode and the resistance changing layer where a switching interface is formed. The buffer layer and the resistance changing layer include n-type metal oxides, and materials of the buffer layer and the resistance changing layer are selected such that energy at a bottom of a conduction band of the n-type metal oxide configuring the buffer layer is lower than that of the n-type metal oxide configuring the resistance changing layer.

摘要翻译： 通过抑制伴随着成形处理的完成的尖锐电流，可以稳定地进行具有特性变化的开关动作的可变电阻元件，以及包括该可变电阻元件的非易失性半导体存储器件。 非易失性半导体存储器件使用可变电阻元件来存储在第一电极和第二电极之间插入电阻变化层的信息，并且缓冲层插入在第一电极和电阻变化层之间，其中开关 界面形成。 缓冲层和电阻变化层包括n型金属氧化物，并且选择缓冲层和电阻变化层的材料，使得构成缓冲层的n型金属氧化物的导带的底部的能量为 低于构成电阻变化层的n型金属氧化物。