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    Unlock bypass program mode for non-volatile memory
    1.
    发明授权
    Unlock bypass program mode for non-volatile memory 失效
    为非易失性存储器解锁旁路程序模式

    公开(公告)号：US6157567A

    公开(公告)日：2000-12-05

    申请号：US70160

    申请日：1998-04-30

    申请人： Tiao-Hua Kuo ,  Eric Itakura ,  May Xie ,  Nancy Leong

    发明人： Tiao-Hua Kuo ,  Eric Itakura ,  May Xie ,  Nancy Leong

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/10

    摘要： The invention is directed to a single power supply pin non-volatile memory device that increases programming speed by providing for two-cycle programming. The invention maintains measures to prevent accidental user overwrites and maintains JEDEC standard compatibility. To provide for two-cycle programming, a three-cycle unlock bypass command is first sent, in one embodiment, after which a plurality of consecutive two-cycle program commands can be sent.

    摘要翻译： 本发明涉及通过提供两周期编程来提高编程速度的单个电源引脚非易失性存储器件。 本发明保持措施以防止意外用户重写并维护JEDEC标准的兼容性。 为了提供双周期编程，首先发送三周期解锁旁路命令，在一个实施例中，之后可以发送多个连续的两周期程序命令。

    Fast chip erase mode for non-volatile memory
    2.
    发明授权
    Fast chip erase mode for non-volatile memory 有权
    用于非易失性存储器的快速芯片擦除模式

    公开(公告)号：US6101129A

    公开(公告)日：2000-08-08

    申请号：US291984

    申请日：1999-04-14

    申请人： Johnny Chen ,  Tiao-Hua Kuo ,  Nancy Leong

    发明人： Johnny Chen ,  Tiao-Hua Kuo ,  Nancy Leong

    IPC分类号： G11C16/16 ,  G11C16/04

    CPC分类号： G11C16/16

    摘要： A method for fast chip erase of memory cells in a non-volatile memory array comprises the steps of providing an acceleration voltage greater than the internal pump voltage supplied by a conventional internal voltage supply pump, providing an erase write command, and performing a fast erase operation on the memory cells, comprising the step of coupling the acceleration voltage to the sources of the memory cells in a plurality of sectors simultaneously. In an embodiment, a fast preprogramming operation is performed on the memory cells prior to the step of performing the fast erase operation in the fast chip erase mode. In a further embodiment, a fast weak programming (APDE) operation is performed on the memory cells subsequent to the step of performing the fast erase operation in the fast chip erase mode. In an additional embodiment, the step of performing the fast erase operation further comprises the steps of detecting the acceleration voltage, generating an acceleration voltage indicator signal in response to the detection of the acceleration voltage, and generating a fast chip erase write command in response to the acceleration voltage indicator signal and the erase write command.

    摘要翻译： 用于在非易失性存储器阵列中快速擦除存储器单元的方法包括以下步骤：提供大于由常规内部电压供应泵提供的内部泵浦电压的加速电压，提供擦除写入命令，以及执行快速擦除 包括将加速电压与多个扇区中的存储单元的源极同时耦合的步骤。 在一个实施例中，在以快速擦除擦除模式执行快速擦除操作的步骤之前，对存储器单元执行快速预编程操作。 在另一实施例中，在执行快速擦除擦除模式中的快速擦除操作的步骤之后，对存储器单元执行快速弱编程（APDE）操作。 在另外的实施例中，执行快速擦除操作的步骤还包括以下步骤：检测加速电压，响应于加速电压的检测产生加速电压指示信号，并响应于 加速电压指示信号和擦除写命令。

    Multi-bit flash memory device having improved program rate
    3.
    发明授权
    Multi-bit flash memory device having improved program rate 有权
    具有改进的程序速率的多位闪存设备

    公开(公告)号：US07433228B2

    公开(公告)日：2008-10-07

    申请号：US11229519

    申请日：2005-09-20

    申请人： Tiao-Hua Kuo ,  Nancy Leong ,  Hounien Chen ,  Sachit Chandra ,  Nian Yang

    发明人： Tiao-Hua Kuo ,  Nancy Leong ,  Hounien Chen ,  Sachit Chandra ,  Nian Yang

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0491 ,  G11C16/0475 ,  G11C16/10

    摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.

    摘要翻译： 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储器单元包括衬底，控制栅极，具有用于存储至少两个独立电荷的至少两个电荷存储区域的电荷存储元件，源 区域和漏极区域。 该方法包括将至少一个存储器单元指定为高速存储单元，并且通过将至少两个电荷存储区域中的第一个置于编程状态来预处理高速存储器单元，并且随后使能在 第二个地区的利率要高得多。

    Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture
    5.
    发明授权
    Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture 有权
    银行选择器电路，用于具有灵活的银行分区架构的同时操作的闪存设备

    公开(公告)号：US06633949B2

    公开(公告)日：2003-10-14

    申请号：US09892431

    申请日：2001-06-26

    申请人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

    发明人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

    IPC分类号： G06F1200

    CPC分类号： G11C8/12 ,  G11C16/08

    摘要： A bank selector encoder comprises a partition indicator circuit having a plurality of partition boundary indicator terminals, a plurality of inverters arranged in a plurality of columns, with each column of the inverters coupled to a respective one of a plurality of columns of ROM cells in a ROM array and a plurality of bank selector code outputs coupled to respective columns of the inverters. The partition boundary indicator terminals are capable of designating a memory partition boundary to identify an upper memory bank and a lower memory bank. The bank selector encoder is capable of generating an identifying bank selector code for each of a plurality of the predetermined memory partition boundaries. The bank selector encoder outputs code bits of a bank selector code based upon the partition boundary indicator terminals.

    摘要翻译： 存储体选择器编码器包括具有多个分区边界指示符终端的分区指示器电路，多列排列的多个反相器，其中每列反相器耦合到多列ROM单元的相应一列 ROM阵列和耦合到反相器的各列的多个存储体选择器代码输出。 分区边界指示符终端能够指定存储器分区边界以识别上部存储体和下部存储体。 存储体选择器编码器能够为多个预定的存储分区边界中的每一个生成识别库选择器代码。 存储体选择器编码器基于分区边界指示符终端输出存储体选择器代码的代码位。

    Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture
    6.
    发明授权
    Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture 有权
    银行选择器电路，用于具有灵活的银行分区架构的同时操作的闪存设备

    公开(公告)号：US06275894B1

    公开(公告)日：2001-08-14

    申请号：US09159489

    申请日：1998-09-23

    申请人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

    发明人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

    IPC分类号： G11C1604

    CPC分类号： G11C8/12 ,  G11C16/08

    摘要： A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option 18, a bank selector encoder 2 coupled to receive a memory partition indicator signal from the memory boundary option 18, and a bank selector decoder 3 coupled to receive a bank selector code from the bank selector encoder 2. The decoder 3, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

    摘要翻译： 一种用于具有灵活存储体分区架构的同步操作闪速存储器件的存储体选择器电路包括存储器边界选项18，耦合以从存储器边界选项18接收存储器分区指示符信号的存储体选择器编码器2以及存储体选择器解码器3 耦合以从存储体选择器编码器2接收存储体选择器代码。解码器3在接收到存储器地址时输出存储体选择器输出信号，以将同时操作中的存储器地址指向下存储体或较高存储体 闪存设备，根据所选择的内存分区边界。

    Simultaneous operation flash memory device with a flexible bank partition architecture
    7.
    发明授权
    Simultaneous operation flash memory device with a flexible bank partition architecture 有权
    具有灵活的银行分区体系结构的同步操作闪存设备

    公开(公告)号：US5995415A

    公开(公告)日：1999-11-30

    申请号：US159142

    申请日：1998-09-23

    申请人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

    发明人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

    IPC分类号： G11C16/02 ,  G11C7/18 ,  G11C8/12 ,  G11C16/06 ,  G11C16/08 ,  G11C7/00

    CPC分类号： G11C16/08 ,  G11C7/18 ,  G11C8/12

    摘要： A simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises a memory array 20 including a plurality of memory cells arranged in a plurality of columns and rows, a plurality of bit lines 28 and 30 each coupled to a respective column of the memory cells, each of the bit lines comprising first and second bit line segments separated by a gap designating a memory partition boundary between upper and lower memory banks, and an X-decoder 22 coupled to the respective rows of the memory cells to row decode the memory array in response to receiving upper and lower bank memory addresses. Two pre-decoders 24 and 26 are coupled to the X-decoder 22. Two Y-decoders 32 and 34 are coupled to the bit line segments to provide column decoding for the memory cells in the upper and lower memory banks, respectively.

    摘要翻译： 具有柔性库分隔体系结构的同时操作的非易失性存储器件包括存储器阵列20，存储器阵列20包括布置在多个列和行中的多个存储器单元，多个位线28和30，每个位线连接到相应的列 存储器单元，每个位线包括由指定上存储体和下存储体之间的存储器分区边界的间隙分隔的第一和第二位线段，以及耦合到存储器单元的各行的X解码器22进行行解码 存储器阵列响应于接收上部和下部存储器地址。 两个预解码器24和26耦合到X解码器22.两个Y解码器32和34分别耦合到位线段以对上和下存储体中的存储单元提供列解码。

    Multi-bit flash memory device having improved program rate
    9.
    发明申请
    Multi-bit flash memory device having improved program rate 有权
    具有改进的程序速率的多位闪存设备

    公开(公告)号：US20070064480A1

    公开(公告)日：2007-03-22

    申请号：US11229519

    申请日：2005-09-20

    申请人： Tiao-Hua Kuo ,  Nancy Leong ,  Hounien Chen ,  Sachit Chandra ,  Nian Yang

    发明人： Tiao-Hua Kuo ,  Nancy Leong ,  Hounien Chen ,  Sachit Chandra ,  Nian Yang

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0491 ,  G11C16/0475 ,  G11C16/10

    摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.

    摘要翻译： 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储器单元包括衬底，控制栅极，具有用于存储至少两个独立电荷的至少两个电荷存储区域的电荷存储元件，源 区域和漏极区域。 该方法包括将至少一个存储器单元指定为高速存储单元，并且通过将至少两个电荷存储区域中的第一个置于编程状态来预处理高速存储器单元，并且随后使能在 第二个地区的利率要高得多。

    Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture
    10.
    发明授权
    Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture 失效
    银行选择器电路，用于具有灵活的银行分区架构的同时操作的闪存设备

    公开(公告)号：US06470414B2

    公开(公告)日：2002-10-22

    申请号：US09893247

    申请日：2001-06-26

    申请人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

    发明人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

    IPC分类号： G06F1200

    CPC分类号： G11C8/12 ,  G11C16/08

    摘要： A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option, a bank selector encoder coupled to receive a memory partition indicator signal from the memory boundary option, and a bank selector decoder coupled to receive a bank selector code from the bank selector encoder. The decoder, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

    摘要翻译： 一种用于具有灵活存储区划分架构的同步操作闪速存储器件的存储体选择器电路，包括存储器边界选项，耦合以从存储器边界选项接收存储器分区指示符信号的存储体选择器编码器，以及耦合以接收 来自银行选择器编码器的存储体选择器代码。 解码器在接收到存储器地址时输出存储体选择器输出信号，以根据选择的存储器分区边界将存储器地址指向同时操作闪速存储器件中的下部存储器组或上部存储器组。