公开(公告)号：US20080290892A1

公开(公告)日：2008-11-27

申请号：US11946426

申请日：2007-11-28

申请人： Toru TAKEGUCHI ,  Kaoru Motonami

发明人： Toru TAKEGUCHI ,  Kaoru Motonami

IPC分类号： G01R31/26

CPC分类号： H01L27/1255 ,  G02F2001/136254 ,  G02F2202/104 ,  H01L27/1285

摘要： In an evaluation device a plurality of evaluation cells, a signal wiring for applying a voltage to the evaluation cells, and an output terminal pad for a signal taking out wiring for measuring outputs from the evaluation cells through a signal taking out wiring are provided on an insulating substrate. Thus, the in-plane distribution of electric characteristics can be easily measured. Further, the electric characteristics related to the particle diameter of the crystal of a poly-crystal silicon film are evaluated so that the in-plane unevenness of the particle diameter of the crystal of the poly-crystal silicon film can be managed.

摘要翻译： 在评价装置中，在评价单元上设置用于向评价单元施加电压的信号布线，以及用于通过取出布线的信号从输出检测来自评价单元的信号取出布线的输出端子垫 绝缘基板。 因此，可以容易地测量电特性的面内分布。 此外，评价与多晶硅膜的晶体的粒径有关的电特性，从而可以管理多晶硅膜的晶体的粒径的面内不均匀性。

公开(公告)号：US20080048187A1

公开(公告)日：2008-02-28

申请号：US11836312

申请日：2007-08-09

申请人： Toru TAKEGUCHI ,  Shinsuke Yura

发明人： Toru TAKEGUCHI ,  Shinsuke Yura

IPC分类号： H01L29/06 ,  G21K5/00 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L21/02675 ,  B23K26/064 ,  B23K26/066 ,  B23K26/0738 ,  B23K26/082 ,  B23K26/083 ,  B23K26/40 ,  B23K2101/42 ,  B23K2103/50 ,  H01L21/02532 ,  H01L21/02691 ,  H01L21/2026 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04

摘要： A semiconductor thin film according to an embodiment of the present invention includes: a polycrystallized semiconductor thin film formed by applying laser light to an amorphous semiconductor thin film; and crystal grains arranged into a lattice shape with a size that is about ½ of an oscillation wavelength of the laser light.

摘要翻译： 根据本发明实施例的半导体薄膜包括：通过向非晶半导体薄膜施加激光而形成的多晶半导体薄膜; 以及排列成尺寸为激光的振荡波长的约1/2的晶格形状的晶粒。

公开(公告)号：US20080179600A1

公开(公告)日：2008-07-31

申请号：US11954338

申请日：2007-12-12

申请人： Toru TAKEGUCHI

发明人： Toru TAKEGUCHI

IPC分类号： H01L29/10 ,  H01L21/00

CPC分类号： H01L29/66757 ,  H01L29/78606 ,  H01L29/78675

摘要： It is an object to obtain a display device which has a thin film transistor using a semiconductor film, and in which initial failures are reduced, and a high-resolution display due to miniaturization of the thin film transistor is enabled. In a thin film transistor, a gate electrode 6 is formed above a polycrystalline semiconductor film 4 via a gate insulating film 5. A taper angle θ2 of a section of a pattern end portion of the polycrystalline semiconductor film 4 in a region where the polycrystalline semiconductor film 4 and the gate electrode 6 intersect with each other is smaller than a taper angle θ1 of the other region.

摘要翻译： 本发明的目的是获得具有使用半导体膜的薄膜晶体管的显示装置，其中初始故障降低，并且由于薄膜晶体管的小型化而能够进行高分辨率显示。 在薄膜晶体管中，通过栅极绝缘膜5在多晶半导体膜4的上方形成栅极6.在多晶半导体膜4的多晶半导体膜4的区域中，多晶半导体膜4的图案端部的截面的锥角θ2 半导体膜4和栅电极6彼此相交小于另一区域的锥角θ1。

公开(公告)号：US20110210347A1

公开(公告)日：2011-09-01

申请号：US13032978

申请日：2011-02-23

申请人： Toru TAKEGUCHI

发明人： Toru TAKEGUCHI

IPC分类号： H01L33/08 ,  H01L21/84

CPC分类号： H01L27/124 ,  H01L27/1288 ,  H01L29/66765 ,  H01L29/78606

摘要： A semiconductor device including: a thin film transistor substrate; and a driving circuit, wherein the thin film transistor substrate includes: a thin film transistor includes: a gate electrode; a gate insulating film that is formed on the insulating substrate and the gate electrode; a semiconductor layer that is formed on the gate insulating film; a channel protecting film; and a source electrode and a drain electrode that are formed to connect with the semiconductor layer; and a wiring converting unit that directly and electrically connects a first wiring layer and a second wiring layer through a first contact hole formed in the gate insulating film in the driving circuit, wherein the first wiring layer is formed at the same layer as the gate electrode on the insulating substrate; and wherein the second wiring layer is formed at the same layer as the source electrode and the drain electrode.

摘要翻译： 一种半导体器件，包括：薄膜晶体管衬底; 以及驱动电路，其中所述薄膜晶体管基板包括：薄膜晶体管，包括：栅电极; 形成在绝缘基板和栅电极上的栅极绝缘膜; 形成在所述栅极绝缘膜上的半导体层; 通道保护膜; 以及形成为与半导体层连接的源电极和漏电极; 以及布线转换单元，其通过形成在所述驱动电路中的所述栅极绝缘膜中的第一接触孔来直接和电连接第一布线层和第二布线层，其中所述第一布线层形成在与所述栅电极相同的层 在绝缘基板上; 并且其中所述第二布线层形成在与所述源电极和所述漏电极相同的层。

公开(公告)号：US20100176399A1

公开(公告)日：2010-07-15

申请号：US12684338

申请日：2010-01-08

申请人： Toru TAKEGUCHI

发明人： Toru TAKEGUCHI

IPC分类号： H01L29/786 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L29/78669 ,  H01L21/02532 ,  H01L21/02675 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78678

摘要： A back-channel-etch type TFT includes a gate electrode, an SiN film that is formed on the gate electrode, and an SiO film that is formed and patterned on the SiN film. The TFT further includes an polycrystalline semiconductor film that is formed and patterned on the SiO film in contact with the SiO film in such a way that all pattern ends of the polycrystalline semiconductor film are located in close proximity to pattern ends of the SiO film.

摘要翻译： 背沟道蚀刻型TFT包括栅电极，形成在栅极上的SiN膜和在SiN膜上形成和图案化的SiO膜。 TFT还包括在与SiO膜接触的SiO膜上形成和图案化的多晶半导体膜，使得多晶半导体膜的所有图案端都位于非常接近SiO膜的图案端。