公开(公告)号：US08908117B2

公开(公告)日：2014-12-09

申请号：US13281893

申请日：2011-10-26

申请人： Masami Hayashi ,  Osamu Miyagawa ,  Toru Takeguchi ,  Shinichi Yano ,  Yasuyoshi Itoh ,  Shingo Nagano

发明人： Masami Hayashi ,  Osamu Miyagawa ,  Toru Takeguchi ,  Shinichi Yano ,  Yasuyoshi Itoh ,  Shingo Nagano

IPC分类号： G02F1/136 ,  G02F1/1343 ,  G02F1/1345 ,  H01L27/12 ,  G02F1/1362

CPC分类号： H01L27/124 ,  G02F1/13452 ,  G02F1/136286

摘要： A thin film transistor array substrate of the present invention having an array area, and a frame area, the thin film transistor array substrate includes: a thin film transistor; an upper metal pattern formed by the same material as source and drain electrodes at the same layer; a transparent conductive film pattern; and an upper layer insulation film, wherein the transparent conductive film pattern has: a first-type transparent conductive film pattern provided to located within one of a pattern of the electrode pattern and a pattern of the metal pattern, as viewed from the top side, and to not cover pattern end faces of the electrode pattern or the metal pattern; and a second-type transparent conductive film pattern provided to stick out from an inside of at least a portion of one of the patterns, as viewed from the top side and to cover the pattern end faces.

摘要翻译： 具有阵列区域和框架区域的本发明的薄膜晶体管阵列基板，薄膜晶体管阵列基板包括：薄膜晶体管; 由与同层的源极和漏极相同的材料形成的上部金属图案; 透明导电膜图案; 和上层绝缘膜，其中透明导电膜图案具有：从顶侧观察设置为位于电极图案的图案和金属图案的图案之一内的第一类型透明导电膜图案， 并且不覆盖电极图案或金属图案的图案端面; 以及第二类型的透明导电膜图案，设置成从顶侧观察到从图案的至少一部分的内侧伸出并覆盖图案端面。

公开(公告)号：US08384086B2

公开(公告)日：2013-02-26

申请号：US12888779

申请日：2010-09-23

申请人： Kazushi Yamayoshi ,  Toru Takeguchi ,  Kazutoshi Aoki

发明人： Kazushi Yamayoshi ,  Toru Takeguchi ,  Kazutoshi Aoki

IPC分类号： H01L27/108

CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L29/04 ,  H01L29/66765

摘要： A method of crystallizing an amorphous semiconductor film, the method comprising the steps of: forming a gate electrode on a transparent insulating substrate; forming a gate insulating film on the transparent insulating substrate and on an upper part of the gate electrode; forming an amorphous semiconductor film on the gate insulating film; forming a light-transmissive insulating film on the amorphous semiconductor film; forming a metal film having an opening on the light-transmissive insulating film; irradiating laser light onto both a region of the light-transmissive insulating film exposed by the opening and the metal film, which is used as a mask for shielding the laser light; and performing laser annealing to make the laser light to be absorbed through the light-transmissive insulating film into a region of the amorphous semiconductor film exposed by the opening, so that the amorphous semiconductor film is heated and converted to a crystalline semiconductor film.

摘要翻译： 一种使非晶半导体膜结晶的方法，所述方法包括以下步骤：在透明绝缘基板上形成栅电极; 在透明绝缘基板上和栅电极的上部形成栅极绝缘膜; 在栅极绝缘膜上形成非晶半导体膜; 在所述非晶半导体膜上形成透光绝缘膜; 在所述透光绝缘膜上形成具有开口的金属膜; 将激光照射到由开口曝光的透光绝缘膜的区域和用作屏蔽激光的掩模的金属膜; 并且进行激光退火以使激光通过透光绝缘膜吸收到由开口暴露的非晶半导体膜的区域中，使得非晶半导体膜被加热并转换成结晶半导体膜。

公开(公告)号：US07683977B2

公开(公告)日：2010-03-23

申请号：US11830474

申请日：2007-07-30

申请人： Hitoshi Nagata ,  Toru Takeguchi

发明人： Hitoshi Nagata ,  Toru Takeguchi

IPC分类号： H01L27/105 ,  H01L21/84

CPC分类号： G02F1/1368 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908

摘要： A wiring layer includes a signal line and covers a predetermined portion on a source region and a drain region of a crystalline silicon layer. A gate insulating layer is on the crystalline silicon layer and the wiring layer. A gate electrode layer above the gate insulating layer includes a scanning line, a gate electrode corresponding to a channel region of the crystalline silicon layer, and a capacitor electrode corresponding to a predetermined portion of the wiring layer. The capacitor electrode is formed separately from the scanning line and the gate electrode and is configured to form a capacitor with the wiring layer. An interlayer insulating film is on the gate electrode layer and the gate insulating layer. A pixel electrode layer on the interlayer insulating film includes a pixel electrode connected to the wiring layer through a contact hole in the gate insulating layer and the interlayer insulating film.

摘要翻译： 布线层包括信号线并且覆盖晶体硅层的源极区域和漏极区域上的预定部分。 栅极绝缘层在晶体硅层和布线层上。 栅极绝缘层上方的栅电极层包括扫描线，对应于晶体硅层的沟道区的栅电极和对应于布线层的预定部分的电容电极。 电容电极与扫描线和栅电极分开形成，并与配线层形成电容器。 层间绝缘膜位于栅极电极层和栅极绝缘层上。 层间绝缘膜上的像素电极层包括通过栅极绝缘层和层间绝缘膜中的接触孔与布线层连接的像素电极。

公开(公告)号：US07420215B2

公开(公告)日：2008-09-02

申请号：US11767217

申请日：2007-06-22

申请人： Kazunori Inoue ,  Nobuaki Ishiga ,  Kensuke Nagayama ,  Toru Takeguchi ,  Kazumasa Kawase

发明人： Kazunori Inoue ,  Nobuaki Ishiga ,  Kensuke Nagayama ,  Toru Takeguchi ,  Kazumasa Kawase

IPC分类号： H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H01L29/10 ,  H01L31/0376 ,  H01L31/20 ,  H01L31/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01J29/28 ,  G02F1/13439 ,  G02F1/13458 ,  H01L27/3244 ,  H01L51/5206 ,  H01L51/5218 ,  H01L51/5234 ,  H01L2227/323

摘要： A transparent conductive film substantially made from In2O3, SnO2 and ZnO, having a molar ratio In/(In+Sn+Zn) of 0.65 to 0.8 and also a molar ratio Sn/Zn of 1 or less: The transparent conductive film has a favorable electric contact property with an electrode or line made from Al or Al alloy film. Further, a semiconductor device having an electrode or line made from the transparent conductive film has high reliability and productivity.

摘要翻译： 基本上由In 2 N 3 O 3，SnO 2和ZnO组成的透明导电膜，其具有In /（In + Sn + Zn ）为0.65〜0.8，Sn / Zn的摩尔比为1以下：透明导电膜与由Al或Al合金膜形成的电极或线具有良好的电接触性。 此外，具有由透明导电膜制成的电极或线的半导体器件具有高的可靠性和生产率。

公开(公告)号：US20080179600A1

公开(公告)日：2008-07-31

申请号：US11954338

申请日：2007-12-12

申请人： Toru TAKEGUCHI

发明人： Toru TAKEGUCHI

IPC分类号： H01L29/10 ,  H01L21/00

CPC分类号： H01L29/66757 ,  H01L29/78606 ,  H01L29/78675

摘要： It is an object to obtain a display device which has a thin film transistor using a semiconductor film, and in which initial failures are reduced, and a high-resolution display due to miniaturization of the thin film transistor is enabled. In a thin film transistor, a gate electrode 6 is formed above a polycrystalline semiconductor film 4 via a gate insulating film 5. A taper angle θ2 of a section of a pattern end portion of the polycrystalline semiconductor film 4 in a region where the polycrystalline semiconductor film 4 and the gate electrode 6 intersect with each other is smaller than a taper angle θ1 of the other region.

摘要翻译： 本发明的目的是获得具有使用半导体膜的薄膜晶体管的显示装置，其中初始故障降低，并且由于薄膜晶体管的小型化而能够进行高分辨率显示。 在薄膜晶体管中，通过栅极绝缘膜5在多晶半导体膜4的上方形成栅极6.在多晶半导体膜4的多晶半导体膜4的区域中，多晶半导体膜4的图案端部的截面的锥角θ2 半导体膜4和栅电极6彼此相交小于另一区域的锥角θ1。

公开(公告)号：US20080135909A1

公开(公告)日：2008-06-12

申请号：US11948377

申请日：2007-11-30

申请人： Toru Takeguchi ,  Takuji Imamura ,  Kazushi Yamayoshi ,  Tomoyuki Irizumi ,  Atsunori Nishiura ,  Kaoru Motonami

发明人： Toru Takeguchi ,  Takuji Imamura ,  Kazushi Yamayoshi ,  Tomoyuki Irizumi ,  Atsunori Nishiura ,  Kaoru Motonami

IPC分类号： H01L27/108 ,  H01L21/02

CPC分类号： H01L28/60 ,  G02F1/136213 ,  G02F1/136227 ,  H01L27/1255 ,  H01L27/1288

摘要： In a thin film transistor using a polycrystalline semiconductor film, when a storage capacitor is formed, it is often that a polycrystalline semiconductor film is used also in one electrode of the capacity. In a display device having a storage capacitor and thin film transistor which have a polycrystalline semiconductor film, the storage capacitor exhibits a voltage dependency due to the semiconductor film, and hence a display failure is caused. In the display device of the invention, a metal conductive film 5 is stacked above a semiconductor layer 4d made of a polycrystalline semiconductor film which is used as a lower electrode of a storage capacitor 130.

摘要翻译： 在使用多晶半导体膜的薄膜晶体管中，当形成存储电容时，通常多晶半导体膜也用于一个容量的电极中。 在具有具有多晶半导体膜的存储电容器和薄膜晶体管的显示装置中，存储电容器由于半导体膜而呈现电压依赖性，因此导致显示不良。 在本发明的显示装置中，金属导电膜5层叠在用作保持电容器130的下电极的多晶半导体膜的半导体层4d的上方。

公开(公告)号：US20060284550A1

公开(公告)日：2006-12-21

申请号：US11450332

申请日：2006-06-12

申请人： Toru Takeguchi ,  Osamu Miyakawa

发明人： Toru Takeguchi ,  Osamu Miyakawa

IPC分类号： H01J1/62 ,  G09G3/36

CPC分类号： H01L29/78696 ,  H01L27/0203 ,  H01L27/1296 ,  H01L29/78666

摘要： A thin film transistor includes: an insulation substrate; a semiconductor layer formed on the insulation substrate including, conductive regions that includes impurity, and a channel region sandwiched between the conductive regions; an insulation layer that covers the semiconductor layer; a gate electrode that is formed on the insulator layer at a position where opposes the channel region; and a source electrode and a drain electrode connected to the conductive regions. The channel region divided into a plurality of channel regions and each of channel widths of the plurality of channel regions is in a range from 5 μm to 30 μm.

摘要翻译： 薄膜晶体管包括：绝缘基板; 形成在所述绝缘基板上的包括包含杂质的导电区域和夹在所述导电区域之间的沟道区域的半导体层; 覆盖半导体层的绝缘层; 在与所述沟道区域相对的位置处形成在所述绝缘体层上的栅电极; 以及连接到导电区域的源电极和漏电极。 被分成多个通道区域的通道区域和多个通道区域的每个通道宽度在5μm到30μm的范围内。

公开(公告)号：US20120112194A1

公开(公告)日：2012-05-10

申请号：US13232251

申请日：2011-09-14

申请人： Takeshi Ono ,  Naoki Nakagawa ,  Yusuke Yamagata ,  Kazunori Inoue ,  Nobuaki Ishiga ,  Kensuke Nagayama ,  Naoki Tsumura ,  Toru Takeguchi

发明人： Takeshi Ono ,  Naoki Nakagawa ,  Yusuke Yamagata ,  Kazunori Inoue ,  Nobuaki Ishiga ,  Kensuke Nagayama ,  Naoki Tsumura ,  Toru Takeguchi

IPC分类号： H01L33/08

CPC分类号： H01L29/458 ,  H01L29/42384 ,  H01L29/66765

摘要： It is an object to provide a technique to improve electric characteristics after a high-temperature treatment even when a high melting point metal barrier layer is not formed. A semiconductor device includes a gate electrode formed on a transparent insulation substrate, a semiconductor layer having a Si semiconductor active film and an ohmic low resistance Si film having an n-type conductivity, being formed in this order on the gate electrode with a gate insulation film interposed between the gate electrode and the semiconductor layer, and the source and drain electrodes directly connected to the semiconductor layer and containing at least aluminum (Al). At least nitrogen (N) is contained in a first region that is in the vicinity of an interface between a side surface of the SI semiconductor active film and the source and drain electrodes.

摘要翻译： 本发明的目的是提供一种即使在没有形成高熔点金属阻挡层的情况下也可以改善高温处理后的电特性的技术。 半导体器件包括形成在透明绝缘基板上的栅极电极，具有Si半导体活性膜的半导体层和具有n型导电性的欧姆低电阻Si膜依次形成在具有栅绝缘层的栅电极上 插入在栅电极和半导体层之间的膜，以及直接连接到半导体层并且至少包含铝（Al）的源极和漏极。 在SI半导体活性膜的侧面与源电极和漏极之间的界面附近的第一区域中至少含有氮（N）。

公开(公告)号：US20110210347A1

公开(公告)日：2011-09-01

申请号：US13032978

申请日：2011-02-23

申请人： Toru TAKEGUCHI

发明人： Toru TAKEGUCHI

IPC分类号： H01L33/08 ,  H01L21/84

CPC分类号： H01L27/124 ,  H01L27/1288 ,  H01L29/66765 ,  H01L29/78606

摘要： A semiconductor device including: a thin film transistor substrate; and a driving circuit, wherein the thin film transistor substrate includes: a thin film transistor includes: a gate electrode; a gate insulating film that is formed on the insulating substrate and the gate electrode; a semiconductor layer that is formed on the gate insulating film; a channel protecting film; and a source electrode and a drain electrode that are formed to connect with the semiconductor layer; and a wiring converting unit that directly and electrically connects a first wiring layer and a second wiring layer through a first contact hole formed in the gate insulating film in the driving circuit, wherein the first wiring layer is formed at the same layer as the gate electrode on the insulating substrate; and wherein the second wiring layer is formed at the same layer as the source electrode and the drain electrode.

摘要翻译： 一种半导体器件，包括：薄膜晶体管衬底; 以及驱动电路，其中所述薄膜晶体管基板包括：薄膜晶体管，包括：栅电极; 形成在绝缘基板和栅电极上的栅极绝缘膜; 形成在所述栅极绝缘膜上的半导体层; 通道保护膜; 以及形成为与半导体层连接的源电极和漏电极; 以及布线转换单元，其通过形成在所述驱动电路中的所述栅极绝缘膜中的第一接触孔来直接和电连接第一布线层和第二布线层，其中所述第一布线层形成在与所述栅电极相同的层 在绝缘基板上; 并且其中所述第二布线层形成在与所述源电极和所述漏电极相同的层。

公开(公告)号：US07709841B2

公开(公告)日：2010-05-04

申请号：US11420956

申请日：2006-05-30

申请人： Yasuyoshi Itoh ,  Toru Takeguchi

发明人： Yasuyoshi Itoh ,  Toru Takeguchi

IPC分类号： H01L29/04

CPC分类号： H01L29/78675 ,  H01L27/1296 ,  H01L29/78666

摘要： An island-like semiconductor layer is formed on a main surface of an insulating substrate. A side wall of the island-like semiconductor layer is made substantially perpendicular to the insulating substrate. An insulating film is formed along the side wall of the semiconductor layer. The insulating film is formed to include a slanted face and have a sectional shape in which a width measured from the side wall of the semiconductor layer decreases as a distance to a bottom increases. A gate insulating film can be formed on the semiconductor layer with good step coverage because of inclusion of the insulating film, to preclude a possibility of causing disconnection of a gate electrode. Also, a thickness of a portion of the semiconductor layer in which a channel region is formed is uniform, to obtain stable transistor characteristics.

摘要翻译： 在绝缘基板的主表面上形成岛状半导体层。 岛状半导体层的侧壁基本上垂直于绝缘基板。 沿半导体层的侧壁形成绝缘膜。 绝缘膜形成为包括倾斜面，并且具有从半导体层的侧壁测量的宽度随着与底部距离的增加而减小的截面形状。 由于包含绝缘膜，可以在半导体层上形成具有良好阶梯覆盖的栅极绝缘膜，以防止导致栅电极断开的可能性。 此外，其中形成沟道区的半导体层的一部分的厚度是均匀的，以获得稳定的晶体管特性。