公开(公告)号：US09748144B1

公开(公告)日：2017-08-29

申请号：US15138228

申请日：2016-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Yi-Wen Chen ,  Chen-Ming Huang ,  Ren-Peng Huang ,  Ching-Fu Lin

IPC: H01L21/00 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/321 ,  H01L21/033 ,  H01L29/51 ,  H01L21/28 ,  H01L27/11

CPC classification number: H01L21/823456 ,  H01L21/0332 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: First and second semiconductor structures, a CESL, and an ILD layer are formed on a substrate. The first semiconductor structure includes first dummy gate, first nitride mask, and first oxide mask. The second semiconductor structure includes second dummy gate, second nitride mask, and second oxide mask. A first planarization is performed to remove a portion of the ILD layer, exposing CESL. A portion of the CESL, a portion of the ILD layer, the first and the second oxide masks are removed. A hard mask layer is formed on the first and the second nitride masks, and in a recess of the ILD layer. A second planarization is performed to remove a portion of the hard mask layer, the first and the second nitride masks, exposing first and second dummy gates. A remaining portion of the hard mask layer covers the ILD layer.