公开(公告)号：US09929056B1

公开(公告)日：2018-03-27

申请号：US15359389

申请日：2016-11-22

Applicant: United Microelectronics Corp.

Inventor： Te-Chiu Tsai ,  Shih-Yin Hsiao ,  Ching-Wei Teng ,  Tun-Jen Cheng ,  Hung-Yi Tsai ,  Shan-Shi Huang

IPC: H01L21/3205 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/823462 ,  H01L21/32 ,  H01L21/823456

Abstract: A method for forming gate structures for a HV device and a MV device is provided. The method includes forming a HV oxide layer on the substrate, covering a first region predetermined for forming the HV device. Further in the method, a dielectric mask is formed on a central portion of the HV oxide layer. A thermal oxidation process is performed to form a MV oxide layer on the substrate at a second region predetermined for forming the MV device, wherein peripheral portions of the HV oxide layer not covered by the dielectric mask grow thicker. The dielectric mask is removed. A conductive layer is formed over the substrate. The conductive layer, the HV oxide layer, the MV oxide layer are patterned to form the gate structures.

公开(公告)号：US20250048671A1

公开(公告)日：2025-02-06

申请号：US18459454

申请日：2023-09-01

Applicant: United Microelectronics Corp.

Inventor： Hsuan-Kai Chen ,  Tun-Jen Cheng ,  Ching-Chung Yang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chiu-Te Lee

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423

Abstract: A transistor structure including a substrate, a gate dielectric layer, a gate, a first doped region, a second doped region, a first drift region, and a dummy gate is provided. The gate dielectric layer is located on the substrate. The gate dielectric layer includes first and second portions. The second portion is connected to the first portion. The thickness of the second portion is greater than the thickness of the first portion. The gate is located on the first and second portions. The first doped region and the second doped region are located in the substrate on two sides of the gate dielectric layer. The first drift region is located in the substrate on one side of the gate. The second doped region is located in the first drift region. The dummy gate is located on the second portion between the gate and the second doped region.

公开(公告)号：US10008573B1

公开(公告)日：2018-06-26

申请号：US15450030

申请日：2017-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Hsuan-Kai Chen ,  Tun-Jen Cheng

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/404 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/7833 ,  H01L29/7835

Abstract: A high-voltage metal-oxide-semiconductor transistor device includes a semiconductor substrate, a gate structure, a first drift region, a first isolation structure, a drain region, and a first sub-gate structure. The gate structure and the first sub-gate structure are disposed on the semiconductor substrate and separated from each other. The first drift region is disposed in the semiconductor substrate and disposed at one side of the gate structure. The first isolation structure and the drain region are disposed in the first drift region and separated from each other. A part of the first drift region is disposed between the drain region and the first isolation structure. The first sub-gate structure is at least partially disposed on the first drift region disposed between the drain region and the first isolation structure, and the first sub-gate structure is electrically connected to the drain region.

公开(公告)号：US09570451B1

公开(公告)日：2017-02-14

申请号：US15151483

申请日：2016-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Tun-Jen Cheng

IPC: H01L21/338 ,  H01L27/11 ,  H01L21/266 ,  H01L21/027 ,  H01L21/265

CPC classification number: H01L27/1116 ,  H01L21/0273 ,  H01L21/26586 ,  H01L21/823412 ,  H01L27/1104 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66492

Abstract: A method of forming semiconductor devices. First, a substrate is provided, and a first implant area and a second implant area are defined in a mask pattern. Subsequently, a resist layer on the substrate is patterned using the mask pattern to form a first opening exposing the first implant area and a second opening to expose the second implant area. After that, an ion implantation process including a partial shadowing ion implant is processed, wherein the second implant area is implanted by the partial shadowing ion implant to a predetermined concentration, and the first implant area is substantially not implanted by the partial shadowing ion implant.

Abstract translation: 一种形成半导体器件的方法。 首先，提供基板，并且以掩模图案限定第一注入区域和第二注入区域。 随后，使用掩模图案对衬底上的抗蚀剂层进行构图，以形成暴露第一注入区域的第一开口和暴露第二注入区域的第二开口。 之后，处理包括部分阴离子离子注入的离子注入工艺，其中通过部分阴离子注入将第二注入区植入预定浓度，并且第一注入区基本上不被部分阴离子注入植入。