公开(公告)号：US20250079168A1

公开(公告)日：2025-03-06

申请号：US18378666

申请日：2023-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ta-Wei Chiu ,  Ping-Hung Chiang ,  Shin-Hung Li ,  Shan-Shi Huang

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a first oxide layer and a second oxide layer. The substrate has a first region and a second region. The first oxide layer is disposed on the first region. The first oxide layer includes a first thermal oxide layer and a first deposited oxide layer, and a portion of the first thermal oxide layer is formed by a pad oxide layer. The second oxide layer is disposed on the second region. The second oxide layer includes a second thermal oxide layer and a second deposited oxide layer.

公开(公告)号：US20150079754A1

公开(公告)日：2015-03-19

申请号：US14548248

申请日：2014-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chung Wang ,  Wei-Lun Hsu ,  Shan-Shi Huang ,  Ke-Feng Lin ,  Te-Yuan Wu

IPC: H01L29/66 ,  H01L21/033 ,  H01L29/08 ,  H01L21/266 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/66681 ,  H01L21/0334 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7816

Abstract: The present invention provides a method of fabricating a HV MOS transistor device, including forming a deep well in a substrate, and the deep well; forming a first doped region in the deep well, and the first doped region, wherein a doping concentration of the first doped region and a doping concentration of the deep well in at least one electric field concentration region has a first ratio, the doping concentration of the first doped region and the doping concentration of the deep well outside the electric field concentration region has a second ratio, and the first ratio is greater than the second ratio; and forming a high voltage well in the substrate, and forming a second doped region and a third doped region respectively in the deep well and in the high voltage well.

Abstract translation: 本发明提供一种制造HV MOS晶体管器件的方法，包括在衬底和深阱中形成深阱; 在所述深阱中形成第一掺杂区域和所述第一掺杂区域，其中所述第一掺杂区域的掺杂浓度和所述深阱在至少一个电场浓度区域中的掺杂浓度具有第一比率，所述第一掺杂区域的掺杂浓度 第一掺杂区域和电场浓度区外的深阱的掺杂浓度具有第二比例，第一比值大于第二比例; 以及在所述衬底中形成高电压阱，以及分别在所述深阱和所述高电压阱中形成第二掺杂区和第三掺杂区。

公开(公告)号：US20240429220A1

公开(公告)日：2024-12-26

申请号：US18224057

申请日：2023-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Wen-Fang Lee ,  Shan-Shi Huang ,  Kuan-Chuan Chen

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: The invention provides a semiconductor structure, which comprises a first silicon substrate with a display region and a driving region defined thereon, a circuit layer located on the first silicon substrate, a plurality of light emitting elements located on the display region of the first silicon substrate, a driving chip located on the driving region of the first silicon substrate and electrically connected with the circuit layer, and a second silicon substrate located on the driving chip.

公开(公告)号：US09034713B2

公开(公告)日：2015-05-19

申请号：US14548248

申请日：2014-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chung Wang ,  Wei-Lun Hsu ,  Shan-Shi Huang ,  Ke-Feng Lin ,  Te-Yuan Wu

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08 ,  H01L21/266 ,  H01L21/033

CPC classification number: H01L29/66681 ,  H01L21/0334 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7816

Abstract: The present invention provides a method of fabricating a HV MOS transistor device, including forming a deep well in a substrate, and the deep well; forming a first doped region in the deep well, and the first doped region, wherein a doping concentration of the first doped region and a doping concentration of the deep well in at least one electric field concentration region has a first ratio, the doping concentration of the first doped region and the doping concentration of the deep well outside the electric field concentration region has a second ratio, and the first ratio is greater than the second ratio; and forming a high voltage well in the substrate, and forming a second doped region and a third doped region respectively in the deep well and in the high voltage well.

Abstract translation: 本发明提供一种制造HV MOS晶体管器件的方法，包括在衬底和深阱中形成深阱; 在所述深阱中形成第一掺杂区域和所述第一掺杂区域，其中所述第一掺杂区域的掺杂浓度和所述深阱在至少一个电场浓度区域中的掺杂浓度具有第一比率，所述第一掺杂区域的掺杂浓度 第一掺杂区域和电场浓度区外的深阱的掺杂浓度具有第二比例，第一比值大于第二比例; 以及在所述衬底中形成高电压阱，以及分别在所述深阱和所述高电压阱中形成第二掺杂区和第三掺杂区。

公开(公告)号：US20250102922A1

公开(公告)日：2025-03-27

申请号：US18382528

申请日：2023-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Ruei-Jhe Tsao ,  Shan-Shi Huang ,  Wen-Fang Lee ,  Chiu-Te Lee

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/033

Abstract: The invention provides an exposure method of semiconductor patterns, which comprises the following steps: providing a substrate, performing a first exposure step with a first photomask, forming a first pattern in a first region on the substrate, and performing a second exposure step with a second photomask, forming a second pattern in a second region on the substrate, the first pattern and the second pattern are in contact with each other, and at an interface of the first region And the second region, the first pattern and the second pattern are aligned with each other.

公开(公告)号：US11495681B2

公开(公告)日：2022-11-08

申请号：US17067775

申请日：2020-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Shin-Hung Li ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chiu-Te Lee ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chia-Jung Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28

Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.

公开(公告)号：US20220085210A1

公开(公告)日：2022-03-17

申请号：US17067775

申请日：2020-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Shin-Hung Li ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chiu-Te Lee ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chia-Jung Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.

公开(公告)号：US09929056B1

公开(公告)日：2018-03-27

申请号：US15359389

申请日：2016-11-22

Applicant: United Microelectronics Corp.

Inventor： Te-Chiu Tsai ,  Shih-Yin Hsiao ,  Ching-Wei Teng ,  Tun-Jen Cheng ,  Hung-Yi Tsai ,  Shan-Shi Huang

IPC: H01L21/3205 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/823462 ,  H01L21/32 ,  H01L21/823456

Abstract: A method for forming gate structures for a HV device and a MV device is provided. The method includes forming a HV oxide layer on the substrate, covering a first region predetermined for forming the HV device. Further in the method, a dielectric mask is formed on a central portion of the HV oxide layer. A thermal oxidation process is performed to form a MV oxide layer on the substrate at a second region predetermined for forming the MV device, wherein peripheral portions of the HV oxide layer not covered by the dielectric mask grow thicker. The dielectric mask is removed. A conductive layer is formed over the substrate. The conductive layer, the HV oxide layer, the MV oxide layer are patterned to form the gate structures.

公开(公告)号：US20250072091A1

公开(公告)日：2025-02-27

申请号：US18465183

申请日：2023-09-12

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li ,  Shan-Shi Huang

IPC: H01L29/423

Abstract: Provided is a transistor structure including a gate, a gate dielectric layer, a source region and a drain region. The gate is disposed on a substrate. The gate dielectric layer is disposed between the gate and the substrate. The source region and the drain region are respectively disposed at two opposite sides of the gate. From a top view above the substrate, the gate has two opposite edges in a first direction intersecting a second direction where a channel length of the transistor structure is located, and each of the two opposite edges has a non-linear shape.

公开(公告)号：US20250031438A1

公开(公告)日：2025-01-23

申请号：US18908700

申请日：2024-10-07

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Wen-Fang Lee

IPC: H01L27/085

Abstract: A semiconductor structure includes a substrate comprising a first well region of a first conductive type, a second well region of a second conductive type, and a junction between the first well region and the second well region, wherein the first conductive type and the second conductive type are complementary. An isolation structure is formed in the substrate to define a plurality of first dummy diffusions and second dummy diffusions and at least a first active region in the first well region, wherein the first dummy diffusions are adjacent to the junction, the first dummy diffusions are between the second dummy diffusions and the first active region, and wherein the second dummy diffusions respectively comprise a metal silicide portion. A plurality of first dummy gates are disposed on the first dummy diffusions and completely cover the first dummy diffusions, respectively.