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    LAYOUT PATTERN FOR STATIC RANDOM ACCESS MEMORY
    1.
    发明申请
    LAYOUT PATTERN FOR STATIC RANDOM ACCESS MEMORY 审中-公开

    公开(公告)号：US20200027869A1

    公开(公告)日：2020-01-23

    申请号：US16101528

    申请日：2018-08-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shu-Wei Yeh ,  Chang-Hung Chen

    IPC: H01L27/02 ,  G11C11/412 ,  G11C8/16 ,  G11C11/417 ,  H01L27/11

    Abstract: The present invention provides a layout pattern of a static random access memory (SRAM), comprising at least one substrate, two SRAM units on the substrate, respectively located in a first region and a second region which is adjacent to the first region. Each of the SRAM units includes a first inverter coupled to a second inverter and configured to form a latching circuit, the first inverter includes a first pull-up transistor (PU1) and a first pull-down transistor (PD1), the second inverter includes a second pull-up transistor (PU2) and a second pull-down transistor (PD2). A dummy layer crossing the first a region and the second region, and between the PD1 in the first region and the PD1 in the second region, and a contact structure on the dummy layer, electrically connected to a voltage source Vss.

    Layout pattern of static random access memory and the manufacturing method thereof
    4.
    发明申请
    Layout pattern of static random access memory and the manufacturing method thereof 有权

    公开(公告)号：US20220216220A1

    公开(公告)日：2022-07-07

    申请号：US17163571

    申请日：2021-02-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Chi Lee ,  Shu-Wei Yeh ,  Chang-Hung Chen

    IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238

    Abstract: A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PG1 and the fin structure of the second read transistor RPG.

    Layout pattern for 8T-SRAM and the manufacturing method thereof
    9.
    发明授权
    Layout pattern for 8T-SRAM and the manufacturing method thereof 有权
    8T-SRAM的布局图及其制造方法

    公开(公告)号：US09401366B1

    公开(公告)日：2016-07-26

    申请号：US14792636

    申请日：2015-07-07

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tien-Yu Lu ,  Chang-Hung Chen ,  Yu-Tse Kuo ,  Chun-Hsien Huang

    IPC: G11C11/00 ,  H01L27/088 ,  H01L27/11 ,  H01L27/02 ,  H01L29/06 ,  G11C11/412 ,  H01L21/84 ,  H01L27/105 ,  H01L29/423

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/4125 ,  H01L21/845 ,  H01L27/1052 ,  H01L29/42392

    Abstract: The present invention provides a layout pattern of an 8-transistor static random access memory (8T-SRAM), at least including a first diffusion region, a second diffusion region and a third diffusion region disposed on a substrate, a critical dimension region being disposed between the first diffusion region and the third diffusion region. The critical dimension region directly contacts the first diffusion region and the third diffusion region, a first extra diffusion region, a second extra diffusion region and a third extra diffusion region disposed surrounding and directly contacting the first diffusion region, the second diffusion region and the third diffusion region respectively. The first, the second and the third extra diffusion region are not disposed within the critical dimension region.

    Abstract translation: 本发明提供了至少包括第一扩散区域，第二扩散区域和设置在衬底上的第三扩散区域的8-晶体管静态随机存取存储器（8T-SRAM）的布局图案，设置临界尺寸区域 在第一扩散区域和第三扩散区域之间。 临界尺寸区域直接接触第一扩散区域和第三扩散区域，第一额外扩散区域，第二额外扩散区域和设置在第一扩散区域，第二扩散区域和第三扩散区域周围并直接接触的第三额外扩散区域 扩散区。 第一，第二和第三附加扩散区域不设置在临界尺寸区域内。

    Static random access memory and its layout pattern
    10.
    发明公开
    Static random access memory and its layout pattern 审中-公开

    公开(公告)号：US20240147683A1

    公开(公告)日：2024-05-02

    申请号：US17994381

    申请日：2022-11-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shu-Wei Yeh ,  Chang-Hung Chen

    IPC: H01L27/11

    CPC classification number: H01L27/1104

    Abstract: The invention provides a layout pattern of static random access memory, which comprises a plurality of fin structures on a substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate. The transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2), a first access transistor (PG1), a second access transistor (PG2), a first read port transistor (RPD) and a second read port transistor (RPG). The gate structure of the first read port transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1), wherein a drain of the first pull-down transistor (PD1) is connected to a first voltage source Vss1, and a drain of the first read port transistor (RPD) is connected to a second voltage source Vss2.

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