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1.发明授权公开(公告)号：US11011535B1
公开(公告)日：2021-05-18
申请号：US16724365
申请日：2019-12-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wang Xiang , Chia-Ching Hsu , Shen-De Wang , Weichang Liu
IPC: H01L27/11568 , H01L27/11573 , H01L27/092 , H01L29/66 , H01L21/8238 , H01L21/02 , H01L21/28 , H01L29/49 , H01L21/3213 , H01L21/027 , H01L29/78 , H01L29/51 , H01L21/311
Abstract: A method of integrating memory and metal-oxide-semiconductor (MOS) processes is provided, including steps of forming an oxide layer and a nitride layer on a substrate, forming a field oxide in a first area by an oxidation process with the nitride layer as a mask, wherein the oxidation process simultaneously forms a top oxide layer on the nitride layer, removing the top oxide layer, the nitride layer and the oxide layer in the first area, forming a polysilicon layer on the substrate, and patterning the polysilicon layer into MOS units in the first area and memory units in a second area.
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公开(公告)号：US20170221913A1
公开(公告)日：2017-08-03
申请号：US15487419
申请日：2017-04-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Ching Hsu , Ko-Chi Chen , Shen-De Wang
IPC: H01L27/11529 , H01L27/11531
CPC classification number: H01L27/11529 , H01L27/11524 , H01L27/11531 , H01L27/11536 , H01L27/11539 , H01L27/11573
Abstract: A method of fabricating a semiconductor device includes providing a substrate with a memory region and a logic region, forming a recess of the substrate in the memory region, forming a non-volatile gate stack in the recess, and forming a logic gate stack in the logic region after forming the non-volatile gate stack.
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公开(公告)号：US20240292765A1
公开(公告)日：2024-08-29
申请号：US18658937
申请日：2024-05-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Ching Hsu , Wang Xiang , Shen-De Wang
CPC classification number: H10N70/841 , H10B63/845 , H10N70/021 , H10N70/066 , H10N70/8833
Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line directly on a first metal structure, a top electrode island disposed beside the bottom electrode line, a resistive material sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island, and a cap layer covering a portion of the first metal structure and under the bottom electrode line.
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公开(公告)号：US20220246845A1
公开(公告)日：2022-08-04
申请号：US17196979
申请日：2021-03-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Ching Hsu , Wang Xiang , Shen-De Wang
Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming said RRAM device.
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公开(公告)号：US10090465B2
公开(公告)日：2018-10-02
申请号：US15359975
申请日：2016-11-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Ching Hsu , Liang Yi , Shen-De Wang , Ko-Chi Chen
IPC: H01L45/00
Abstract: A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (TMO) layer formed on the bottom electrode, a TMO sidewall oxides formed at sidewalls of the TMO layer, a top electrode formed on the TMO layer, and spacers formed on the bottom electrode. The upper conducting layer is formed on the top electrode and electrically connected to the top electrode.
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Patent Agency Ranking
公开(公告)号：US20180205013A1
公开(公告)日：2018-07-19
申请号：US15441261
申请日：2017-02-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Liang Yi , Chia-Ching Hsu , Shen-De Wang , Ko-Chi Chen
CPC classification number: H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1683
Abstract: A method of forming a Resistive Random Access Memory (RRAM) includes the following steps. A first dielectric layer is formed on a first electrode layer. A second dielectric layer having a first trench is formed on the first dielectric layer. Spacers are formed beside sidewalls of the first trench. Apart of the first dielectric layer exposed by the spacers is removed, thereby forming a second trench in the first dielectric layer. A resistance switching material fills in the second trench. The second dielectric layer and the spacers are removed. A second electrode layer is formed on the resistance switching material and the first dielectric layer. The present invention also provides a RRAM formed by said method.
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公开(公告)号：US09859335B1
公开(公告)日：2018-01-02
申请号：US15367690
申请日：2016-12-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Ching Hsu , Liang Yi , Shen-De Wang , Ko-Chi Chen
CPC classification number: H01L27/2463 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1683
Abstract: A semiconductor device includes an interconnection formed above a substrate, and the interconnection comprising interconnect layers respectively buried in dielectric layers; a lower conducting layer formed above the substrate; a memory cell structure formed on the lower conducting layer and buried in one of the dielectric layers; an upper conducting layer formed on the memory cell structure. The memory cell structure includes a bottom electrode formed on and electrically connected to the lower conducting layer; a transitional metal oxide (TMO) layer formed on the bottom electrode; and a top electrode formed on the TMO layer, wherein the upper conducting layer is formed on the top electrode and electrically connected to the top electrode. Also, the lower conducting layer and the upper conducting layer are positioned in the different dielectric layers.
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公开(公告)号：US09806255B1
公开(公告)日：2017-10-31
申请号：US15455142
申请日：2017-03-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Ching Hsu , Liang Yi , Shen-De Wang , Ko-Chi Chen
CPC classification number: H01L45/1233 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/124 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1691
Abstract: A resistive random access memory includes a lower electrode, an upper electrode and a resistive layer between the lower electrode and the upper electrode, wherein the resistive layer includes a constant-resistance portion and a variable-resistance portion surrounding the constant-resistance portion.
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公开(公告)号：US12133479B2
公开(公告)日：2024-10-29
申请号：US17229873
申请日：2021-04-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Ching Hsu
CPC classification number: H10N70/8265 , H10N70/021 , H10N70/245 , H10N70/841 , H10N70/8833
Abstract: A semiconductor memory device includes a substrate, a first dielectric layer on the substrate, a bottom electrode on the first dielectric layer, a second dielectric layer on the first dielectric layer, and a top electrode in the second dielectric layer. The top electrode has a lower portion around the bottom electrode and a tapered upper portion. A third dielectric layer is disposed above the bottom electrode and around the tapered upper portion of the top electrode. A resistive-switching layer is disposed between a sidewall of the bottom electrode and a sidewall of the lower portion of the top electrode and between the third dielectric layer and a sidewall of the tapered upper portion of the top electrode. An air gap is disposed in the third dielectric layer.
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公开(公告)号：US20220310910A1
公开(公告)日：2022-09-29
申请号：US17229873
申请日：2021-04-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Ching Hsu
IPC: H01L45/00
Abstract: A semiconductor memory device includes a substrate, a first dielectric layer on the substrate, a bottom electrode on the first dielectric layer, a second dielectric layer on the first dielectric layer, and a top electrode in the second dielectric layer. The top electrode has a lower portion around the bottom electrode and a tapered upper portion. A third dielectric layer is disposed above the bottom electrode and around the tapered upper portion of the top electrode. A resistive-switching layer is disposed between a sidewall of the bottom electrode and a sidewall of the lower portion of the top electrode and between the third dielectric layer and a sidewall of the tapered upper portion of the top electrode. An air gap is disposed in the third dielectric layer.
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