公开(公告)号：US09978758B1

公开(公告)日：2018-05-22

申请号：US15613103

申请日：2017-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Weichang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Wei Ta ,  Chuan Sun

IPC: H01L27/115 ,  H01L29/423 ,  H01L27/11517 ,  H01L21/283 ,  H01L21/02

CPC classification number: H01L21/0214 ,  H01L21/28282 ,  H01L21/283 ,  H01L27/11568 ,  H01L29/42344

Abstract: A flash memory includes a substrate, a memory gate on the substrate, a charge-storage layer between the memory gate and the substrate, a select gate adjacent to the memory gate, a select gate dielectric layer between the select gate and the substrate, a first oxide-nitride spacer between the memory gate and the select gate, and a second oxide-nitride spacer. The select gate includes an upper portion and a lower portion. The second oxide-nitride spacer is disposed between the first oxide-nitride spacer and the upper portion of the select gate.

公开(公告)号：US20210233924A1

公开(公告)日：2021-07-29

申请号：US17229848

申请日：2021-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  Chia-Ching Hsu ,  Shen-De Wang ,  Weichang Liu

IPC: H01L27/11568 ,  H01L21/02 ,  H01L29/51 ,  H01L27/092 ,  H01L29/49 ,  H01L21/027 ,  H01L21/28 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/3213 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.

公开(公告)号：US09455322B1

公开(公告)日：2016-09-27

申请号：US14862118

申请日：2015-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Shan Chiu ,  Shen-De Wang ,  Weichang Liu ,  Wei Ta ,  Zhen Chen ,  Wang Xiang

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/788 ,  H01L27/115 ,  H01L29/51

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881

Abstract: A flash cell forming process includes the following steps. A first gate is formed on a substrate. A first spacer is formed at a side of the first gate, where the first spacer includes a bottom part and a top part. The bottom part is removed, thereby an undercut being formed. A first selective gate is formed beside the first spacer and fills into the undercut. The present invention also provides a flash cell formed by said flash cell forming process. The flash cell includes a first gate, a first spacer and a first selective gate. The first gate is disposed on a substrate. The first spacer is disposed at a side of the first gate, where the first spacer has an undercut at a bottom part, and therefore exposes the substrate. The first selective gate is disposed beside the first spacer and extends into the undercut.

Abstract translation: 闪光单元形成工艺包括以下步骤。 在基板上形成第一栅极。 第一间隔件形成在第一栅极的一侧，其中第一间隔件包括底部和顶部。 底部被去除，从而形成底切。 在第一间隔物旁边形成第一选择栅，并填入底切。 本发明还提供了一种由所述闪存单元形成工艺形成的闪光单元。 闪存单元包括第一栅极，第一间隔物和第一选择栅极。 第一栅极设置在基板上。 第一间隔件设置在第一栅极的一侧，其中第一间隔件在底部具有底切，因此露出基板。 第一选择栅设置在第一间隔物旁边并延伸到底切中。

公开(公告)号：US11444095B2

公开(公告)日：2022-09-13

申请号：US17229848

申请日：2021-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  Chia-Ching Hsu ,  Shen-De Wang ,  Weichang Liu

IPC: H01L29/76 ,  H01L29/66 ,  H01L27/092 ,  H01L27/11568 ,  H01L27/11573 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/311

Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.

公开(公告)号：US10332884B2

公开(公告)日：2019-06-25

申请号：US15802450

申请日：2017-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Che-Jung Hsu ,  Yu-Cheng Tung ,  Jianjun Yang ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  Weichang Liu ,  Shen-De Wang ,  Kok Wun Tan

IPC: H01L27/092 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.

公开(公告)号：US20160049525A1

公开(公告)日：2016-02-18

申请号：US14462550

申请日：2014-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Weichang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wei Ta ,  Yi-Shan Chiu ,  Yuan-Hsiang Chang

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/31105 ,  H01L21/31144 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.

Abstract translation: 闪速存储器结构包括衬底上的存储栅极，与存储栅极相邻的选择栅极以及存储栅极和选择栅极之间的氧化物氮化物间隔物，其中氧化物氮化物间隔物还包括氧化物层和氮化物 层具有上部氮化物部分和下部氮化物部分，并且上部氮化物部分比下部氮化物部分薄。

公开(公告)号：US11011535B1

公开(公告)日：2021-05-18

申请号：US16724365

申请日：2019-12-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  Chia-Ching Hsu ,  Shen-De Wang ,  Weichang Liu

IPC: H01L27/11568 ,  H01L27/11573 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/78 ,  H01L29/51 ,  H01L21/311

Abstract: A method of integrating memory and metal-oxide-semiconductor (MOS) processes is provided, including steps of forming an oxide layer and a nitride layer on a substrate, forming a field oxide in a first area by an oxidation process with the nitride layer as a mask, wherein the oxidation process simultaneously forms a top oxide layer on the nitride layer, removing the top oxide layer, the nitride layer and the oxide layer in the first area, forming a polysilicon layer on the substrate, and patterning the polysilicon layer into MOS units in the first area and memory units in a second area.

公开(公告)号：US09660106B2

公开(公告)日：2017-05-23

申请号：US14462550

申请日：2014-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Weichang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wei Ta ,  Yi-Shan Chiu ,  Yuan-Hsiang Chang

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/31105 ,  H01L21/31144 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.