公开(公告)号：US20220230689A1

公开(公告)日：2022-07-21

申请号：US17151226

申请日：2021-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ning Peng ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang

IPC: G11C16/24 ,  G11C16/08 ,  H01L29/788 ,  H01L27/11556 ,  H01L27/11519

Abstract: An electrically erasable programmable read only memory (EEPROM) includes a substrate, bit lines, a row of erase gate and a row of floating gates. The bit lines are defined in the substrate to extend in a first direction. The row of erase gate having a wave shape is disposed across the bit lines. The row of floating gates having staggered islands is disposed parallel to the row of erase gate. A method of forming said electrically erasable programmable read only memory (EEPROM) is also provided.

公开(公告)号：US10796752B2

公开(公告)日：2020-10-06

申请号：US16290950

申请日：2019-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Ting Chen ,  Hsueh-Chun Hsiao

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

Abstract: A static random access memory cell includes first and second cross-coupled inverters, a write transistor and a read transistor. The first inverter has a first latch node and the second inverter has a second latch node. The write transistor is coupled in series with a wordline transistor between the first latch node of the first inverter and a bitline. The read transistor is coupled between the bitline and a reference terminal and has a control terminal coupled to the first latch node of the first inverter. A method of operating the static random access memory cell includes enabling the wordline transistor during a write operation, and enabling the write transistor during the write operation. The reference terminal is set to floating during the write operation.

公开(公告)号：US20170062279A1

公开(公告)日：2017-03-02

申请号：US14835700

申请日：2015-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sih-Yun Wei ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L21/8238 ,  H01L21/266 ,  H01L27/092 ,  H01L29/66 ,  H01L21/265 ,  H01L29/167

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/6659

Abstract: A transistor set forming process includes the following steps. A substrate having a first area and a second area is provided. An implantation process is performed to form a diffusion region of a first transistor in the substrate of the first area and a channel region of a second transistor in the substrate of the second area at the same time.

Abstract translation: 晶体管组形成工艺包括以下步骤。 提供具有第一区域和第二区域的衬底。 执行注入工艺，以在第一区域的衬底中的第一晶体管的扩散区域和第二区域的衬底中的第二晶体管的沟道区域同时形成。

公开(公告)号：US20240224529A1

公开(公告)日：2024-07-04

申请号：US18608878

申请日：2024-03-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Ting Chen ,  Hsueh-Chun Hsiao

IPC: H10B43/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H10B43/30 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: An SONOS memory cell includes a silicon substrate. A tunnel silicon oxide layer, a silicon nitride layer and a silicon oxide layer are disposed from bottom to top on the silicon substrate. The silicon oxide layer includes two first silicon oxide layers and a second silicon oxide layer. A thickness of the silicon oxide layer is smaller than a thickness of each of the first silicon oxide layers. A control gate covers and contacts the silicon oxide layer. A first source/drain doping region and a second source/drain doping region are respectively disposed at two sides of the control gate. The silicon oxide layer has a cross section. The second silicon oxide layer is sandwiched between the two first silicon oxide layers on the cross section.

公开(公告)号：US20230033836A1

公开(公告)日：2023-02-02

申请号：US17960789

申请日：2022-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

IPC: H01L27/11521 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/78

Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

公开(公告)号：US20200083344A1

公开(公告)日：2020-03-12

申请号：US16123868

申请日：2018-09-06

Applicant: United Microelectronics Corp.

Inventor： Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Chuan-Fu Wang ,  Yu-Huang Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/49 ,  H01L29/45

Abstract: A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided. The first gate structure includes a first gate and a charge storage layer. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate.

公开(公告)号：US20240312527A1

公开(公告)日：2024-09-19

申请号：US18677836

申请日：2024-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ning Peng ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang

IPC: G11C16/24 ,  G11C16/08 ,  H01L29/788 ,  H10B41/10 ,  H10B41/27

CPC classification number: G11C16/24 ,  G11C16/08 ,  H01L29/7881 ,  H10B41/10 ,  H10B41/27

Abstract: A method for forming semiconductor structure with wave shaped erase gate, the method including the steps: forming a floating gate having staggered islands on a substrate, forming a erase gate having a wave shape on the substrate at a first side of the floating gate, and forming a word line having the wave shape on the substrate at a second side of the floating gate opposite to the first side.

公开(公告)号：US12096635B2

公开(公告)日：2024-09-17

申请号：US17722403

申请日：2022-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Ting Chen ,  Hsueh-Chun Hsiao

IPC: H10B43/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H10B43/30 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: An SONOS memory cell includes a silicon substrate. A tunnel silicon oxide layer, a silicon nitride layer and a silicon oxide layer are disposed from bottom to top on the silicon substrate. The silicon oxide layer includes two first silicon oxide layers and a second silicon oxide layer. A thickness of the silicon oxide layer is smaller than a thickness of each of the first silicon oxide layers. A control gate covers and contacts the silicon oxide layer. A first source/drain doping region and a second source/drain doping region are respectively disposed at two sides of the control gate. The silicon oxide layer has a cross section. The second silicon oxide layer is sandwiched between the two first silicon oxide layers on the cross section.

公开(公告)号：US20230309309A1

公开(公告)日：2023-09-28

申请号：US17722403

申请日：2022-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Ting Chen ,  Hsueh-Chun Hsiao

IPC: H01L27/11568 ,  H01L29/423 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L29/4234 ,  H01L29/792 ,  H01L29/40117 ,  H01L29/66833

Abstract: An SONOS memory cell includes a silicon substrate. A tunnel silicon oxide layer, a silicon nitride layer and a silicon oxide layer are disposed from bottom to top on the silicon substrate. The silicon oxide layer includes two first silicon oxide layers and a second silicon oxide layer. A thickness of the silicon oxide layer is smaller than a thickness of each of the first silicon oxide layers. A control gate covers and contacts the silicon oxide layer. A first source/drain doping region and a second source/drain doping region are respectively disposed at two sides of the control gate. The silicon oxide layer has a cross section. The second silicon oxide layer is sandwiched between the two first silicon oxide layers on the cross section.

公开(公告)号：US20150115461A1

公开(公告)日：2015-04-30

申请号：US14066845

申请日：2013-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chou Yu ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/8221 ,  H01L23/544 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2223/54493 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2225/06596

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes following steps. A first wafer is provided, which includes a first region, a second region, and a first semiconductor device disposed in the first region. No semiconductor device is disposed in the second region. A second wafer is provided, which includes a third region, a fourth region and a second semiconductor device disposed in the third region. No semiconductor device is disposed in the fourth region. The first region of the first wafer is overlapped with the fourth region of the second wafer. The second region of the first wafer is overlapped with the third region of the second wafer. A first conductive through via is formed to pass through the fourth region of the second wafer and the first region of the first wafer to electrically connect to the first semiconductor device.

Abstract translation: 提供半导体结构及其形成方法。 该方法包括以下步骤。 提供第一晶片，其包括第一区域，第二区域和设置在第一区域中的第一半导体器件。 在第二区域中不设置半导体器件。 提供第二晶片，其包括设置在第三区域中的第三区域，第四区域和第二半导体器件。 在第四区域中不设置半导体器件。 第一晶片的第一区域与第二晶片的第四区域重叠。 第一晶片的第二区域与第二晶片的第三区域重叠。 形成第一导电通孔以通过第二晶片的第四区域和第一晶片的第一区域以电连接到第一半导体器件。