公开(公告)号：US20180053771A1

公开(公告)日：2018-02-22

申请号：US15238574

申请日：2016-08-16

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

公开(公告)号：US10199385B1

公开(公告)日：2019-02-05

申请号：US15665437

申请日：2017-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Lung Li ,  Ping-Chia Shih ,  Wen-Peng Hsu ,  Chia-Wen Wang ,  Meng-Chun Chen ,  Chih-Hao Pan

IPC: H01L27/115 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.

公开(公告)号：US09966382B2

公开(公告)日：2018-05-08

申请号：US15238574

申请日：2016-08-16

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC: H01L27/115 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/78 ,  H01L27/11573 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11543 ,  H01L27/11563

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

公开(公告)号：US10720440B2

公开(公告)日：2020-07-21

申请号：US15927914

申请日：2018-03-21

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC: H01L27/115 ,  H01L29/66 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/78 ,  H01L27/11573 ,  H01L27/11543 ,  H01L27/11563 ,  H01L21/28 ,  H01L29/788

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

公开(公告)号：US09379128B1

公开(公告)日：2016-06-28

申请号：US14809342

申请日：2015-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Ko-Chi Chen ,  Shen-De Wang ,  Chia-Ching Hsu ,  Chun-Sung Huang ,  Wen-Peng Hsu

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28 ,  H01L21/225

CPC classification number: H01L27/11568 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A split gate NVM device includes a semiconductor substrate, an ONO structure disposed on the semiconductor substrate, a first gate electrode disposed on the ONO structure, a second gate electrode disposed on the semiconductor substrate, adjacent to and insulated from the first gate electrode and the ONO structure, a first doping region with a first conductivity formed in the semiconductor substrate and adjacent to the ONO structure, a second doping region with the first conductivity formed in the semiconductor substrate and adjacent to the second gate electrode, and a third doping region with the first conductivity formed in the semiconductor substrate, disposed between the first doping region and the second doping region and adjacent to the ONO structure and the second gate electrode.

Abstract translation: 分路门NVM器件包括半导体衬底，设置在半导体衬底上的ONO结构，设置在ONO结构上的第一栅电极，设置在半导体衬底上的第二栅极，与第一栅电极相邻并绝缘， ONO结构，在半导体衬底中形成并与ONO结构相邻的具有第一导电性的第一掺杂区，在半导体衬底中形成并与第二栅电极相邻的具有第一导电性的第二掺杂区，以及第三掺杂区， 所述第一导电体形成在所述半导体衬底中，设置在所述第一掺杂区域和所述第二掺杂区域之间并且邻近所述ONO结构和所述第二栅电极。

公开(公告)号：US20190043877A1

公开(公告)日：2019-02-07

申请号：US15665437

申请日：2017-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Lung Li ,  Ping-Chia Shih ,  Wen-Peng Hsu ,  Chia-Wen Wang ,  Meng-Chun Chen ,  Chih-Hao Pan

IPC: H01L27/11568 ,  H01L29/423

Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.

公开(公告)号：US20180211966A1

公开(公告)日：2018-07-26

申请号：US15927914

申请日：2018-03-21

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC: H01L27/1157 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11573 ,  H01L27/11543 ,  H01L29/792 ,  H01L27/11563 ,  H01L29/78

CPC classification number: H01L27/1157 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.