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    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    1.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20150024598A1

    公开(公告)日：2015-01-22

    申请号：US13943900

    申请日：2013-07-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wan-Fang Chung ,  Ping-Chia Shih ,  Hsiang-Chen Lee ,  Che-Hao Chang ,  Jhih-Long Lin ,  Wei-Pin Huang ,  Shao-Nung Huang ,  Yu-Cheng Wang ,  Jaw-Jiun Tu ,  Chung-Che Huang

    IPC: H01L21/306

    CPC classification number: H01L21/306 ,  H01L21/30604 ,  H01L21/31105 ,  H01L21/32139 ,  H01L27/11534 ,  H01L29/66825

    Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.

    Abstract translation: 提供一种制造半导体器件的方法。 提供了具有第一区域和第二多晶硅层的基板，第一区域具有第一多晶硅层和第二区域。 然后在第二区域中的第一区域中的第一多晶硅层的第一多晶硅层之上沉积氮化物HM膜，并在第二区域中的第二多晶硅层上方沉积氮化物HM膜。 之后，在第一区域中的氮化物HM膜上形成第一图案化钝化物以覆盖氮化物HM膜和第一器件，并且在第二区域中的第二多晶硅层之上形成第二图案化钝化。 第二区域中的第二多晶硅层由第二图案化钝化限定。

    Semiconductor device and fabrication method thereof
    4.
    发明申请
    Semiconductor device and fabrication method thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US20140353739A1

    公开(公告)日：2014-12-04

    申请号：US13909057

    申请日：2013-06-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsiang-Chen Lee ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Wan-Fang Chung ,  Yu-Chun Chang ,  Je-Yi Su

    IPC: H01L29/66 ,  H01L29/792

    CPC classification number: H01L29/66833 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/792 ,  H01L29/7923

    Abstract: A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate structure is not less than that of the bottom thereof. A fabrication method thereof is also disclosed. A transient first gate structure and a temporary gate structure are formed by etching through a first hard mask. A second gate structure is formed between a first spacer and a second spacer opposite to each other and disposed respectively on the transient first gate structure and temporary gate structure. The second gate structure is covered with a second hard mask. An etch process is performed through a patterned photoresist layer to remove exposed first hard mask and temporary gate structure and to partially remove exposed portion of first hard mask and transient first gate structure to form the first gate structure.

    Abstract translation: 一种半导体器件，包括彼此紧邻的第一栅极结构和第二栅极结构，其间具有间隔物。 第二栅极结构的顶部的线宽不小于其底部的线宽。 还公开了其制造方法。 通过蚀刻穿过第一硬掩模形成瞬态第一栅极结构和临时栅极结构。 第二栅极结构形成在第一间隔物和彼此相对的第二间隔物之间​​，分别设置在瞬态第一栅极结构和临时栅极结构上。 第二个门结构用第二个硬掩模覆盖。 通过图案化的光致抗蚀剂层进行蚀刻处理以去除暴露的第一硬掩模和临时栅极结构，并且部分地去除第一硬掩模和瞬态第一栅极结构的暴露部分以形成第一栅极结构。

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20140091383A1

    公开(公告)日：2014-04-03

    申请号：US14098290

    申请日：2013-12-05

    Applicant: United Microelectronics Corp.

    Inventor： Ko-Chi Chen ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chi-Cheng Huang ,  Hsiang-Chen Lee

    IPC: H01L29/792 ,  H01L29/78

    CPC classification number: H01L29/792 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7833

    Abstract: A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.

    Abstract translation: 对半导体装置的制造方法进行说明。 堆叠的栅极电介质形成在衬底上，包括从底部到顶部的第一介电层，第二电介质层和第三电介质层。 在堆叠的栅极电介质上形成导电层，然后将其图案化以形成栅极导体。 通过选择性湿式清洗步骤除去第三和第二介电层的暴露部分。 在栅极导体作为掩模的基板中形成S / D延伸区域。 在栅极导体的侧壁上形成第一间隔物，并且去除由第一间隔物露出的第一电介质层的一部分。 在第一间隔物的两侧的基板中形成S / D区域。 在S / D区域上形成金属硅化物层。

    Method for fabricating non-volatile memory semiconductor device
    9.
    发明授权
    Method for fabricating non-volatile memory semiconductor device 有权
    制造非易失性存储器半导体器件的方法

    公开(公告)号：US09129852B1

    公开(公告)日：2015-09-08

    申请号：US14457107

    申请日：2014-08-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsiang-Chen Lee ,  Shao-Nung Huang ,  Wei-Pin Huang ,  Kuo-Lung Li ,  Ling-Hsiu Chou ,  Ping-Chia Shih

    IPC: H01L29/788 ,  H01L27/115

    CPC classification number: H01L27/115 ,  H01L27/11524 ,  H01L27/1157

    Abstract: A method for fabricating a non-volatile memory semiconductor device is disclosed. The method includes the steps of providing a substrate; forming a gate pattern on the substrate, wherein the gate pattern comprises a first polysilicon layer on the substrate, an oxide-nitride-oxide (ONO) stack on the first polysilicon layer, and a second polysilicon layer on the ONO stack; forming an oxide layer on the top surface and sidewall of the gate pattern; performing a first etching process to remove part of the oxide layer; and performing a second etching process to completely remove the remaining oxide layer.

    Abstract translation: 公开了一种用于制造非易失性存储器半导体器件的方法。 该方法包括提供基板的步骤; 在所述衬底上形成栅极图案，其中所述栅极图案包括所述衬底上的第一多晶硅层，所述第一多晶硅层上的氧化物 - 氧化物 - 氧化物（ONO）堆叠以及所述ONO堆叠上的第二多晶硅层; 在栅极图案的顶表面和侧壁上形成氧化物层; 执行第一蚀刻工艺以去除部分氧化物层; 并执行第二蚀刻处理以完全去除剩余的氧化物层。

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