公开(公告)号：US06643201B2

公开(公告)日：2003-11-04

申请号：US10205838

申请日：2002-07-26

申请人： Won-Seok Lee ,  Chang-Yong Lee ,  Jung-Bae Lee ,  Won-Chang Jung

发明人： Won-Seok Lee ,  Chang-Yong Lee ,  Jung-Bae Lee ,  Won-Chang Jung

IPC分类号： G11C700

CPC分类号： G11C7/1069 ,  G11C7/065 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12

摘要： A memory charging circuit includes a read charge control circuit controlled according to a read control signal and an address value. A write charge control circuit is controlled according to a write control signal and the same or a different address value. Charging to and charging from the same data IO lines is controlled using the read charge amplifier circuit and the write charge amplifier circuit. A column select line circuit can be configured into a first arrangement where a first output is activated according to a read control signal and an address and a second output is activated according to a write control signal and the same or a different address. In a second arrangement, the first output is activated according to an address and either the read control signal or the write control signal.

摘要翻译： 存储器充电电路包括根据读取控制信号和地址值控制的读取充电控制电路。 写入充电控制电路根据写入控制信号和相同或不同的地址值进行控制。 使用读取的电荷放大器电路和写入电荷放大器电路来控制对相同数据IO线的充电和充电。 列选择线路电路可以被配置成根据读控制信号和地址激活第一输出的第一布置，并且根据写控制信号和相同或不同的地址来激活第二输出。 在第二布置中，根据地址和读控制信号或写控制信号来激活第一输出。

公开(公告)号：US08395953B2

公开(公告)日：2013-03-12

申请号：US12958726

申请日：2010-12-02

申请人： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

发明人： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C29/025 ,  G11C29/12005 ,  G11C29/1201 ,  G11C2029/1204

摘要： The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a bit-line and a complementary bit-line, and a third test driving voltage having a voltage level of a pre-charge voltage subtracted by the voltage difference in a test mode. The amplifier senses and amplifies a voltage difference between the bit-line and the complementary bit-line.

摘要翻译： 位线读出放大器包括驱动电压控制电路和放大器。 驱动电压控制电路产生具有预充电电压的电压电平的第一测试驱动电压，具有由位线和位线之间的电压差相加的预充电电压的电压电平的第二测试驱动电压 以及第三测试驱动电压，其具有在测试模式下被电压差减去的预充电电压的电压电平。 放大器感测并放大位线和互补位线之间的电压差。

公开(公告)号：US08391095B2

公开(公告)日：2013-03-05

申请号：US12768060

申请日：2010-04-27

申请人： Ho-Cheol Lee ,  Jung-Bae Lee

发明人： Ho-Cheol Lee ,  Jung-Bae Lee

IPC分类号： G11C5/14

CPC分类号： G11C5/148 ,  G11C5/144 ,  G11C5/147 ,  G11C8/16

摘要： Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.

摘要翻译： 公开了一种在多端口半导体存储器中控制深度掉电模式的方法，该多端口半导体存储器具有连接到多个处理器的多个端口。 执行多端口半导体存储器中的深度掉电模式的控制，使得根据通过多个端口中的各个端口施加的信号来确定深度掉电模式的激活/去激活。

公开(公告)号：US08362539B2

公开(公告)日：2013-01-29

申请号：US12458874

申请日：2009-07-27

申请人： Ki-Whan Song ,  Jung-Bae Lee

发明人： Ki-Whan Song ,  Jung-Bae Lee

IPC分类号： H01L27/108

CPC分类号： H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a first substrate including at least one first well region and first impurity regions on portions of the substrate and a bias voltage plate on a surface of the substrate. A semiconductor device may be of a three dimensional stack structure, and in example embodiments, the semiconductor device may further include a through contact plug substantially perpendicularly penetrating at least one substrate and at least one bias voltage plate. Therefore, a design margin of a semiconductor device may be enhanced and a bias voltage may be provided reliably.

摘要翻译： 半导体器件包括：第一衬底，包括至少一个第一阱区域和衬底的部分上的第一杂质区域以及衬底表面上的偏压板。 半导体器件可以是三维堆叠结构，并且在示例性实施例中，半导体器件还可以包括基本垂直地穿透至少一个衬底和至少一个偏置电压板的贯穿接触插塞。 因此，可以提高半导体器件的设计裕度，并且可以可靠地提供偏置电压。

公开(公告)号：US08205135B2

公开(公告)日：2012-06-19

申请号：US13228763

申请日：2011-09-09

申请人： Jung-Bae Lee

发明人： Jung-Bae Lee

IPC分类号： H03M13/00

CPC分类号： G06F11/1008

摘要： A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

摘要翻译： 公开了一种包括存储器控制器和存储器以及相关方法的存储器系统。 该方法包括将与命令相关联的命令和错误检测/校正（EDC）数据从存储器控制器传送到存储器，解码该命令并并行执行与EDC数据相关的EDC操作，并且如果命令是写入 命令，延迟执行由写入命令指示的写入操作，直到完成EDC操作，否则立即执行由命令指示的操作，而不考虑完成EDC操作。

公开(公告)号：US08154934B2

公开(公告)日：2012-04-10

申请号：US12788029

申请日：2010-05-26

申请人： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

发明人： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

摘要： A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.

摘要翻译： 公开了一种半导体存储器件。 半导体器件包括存储单元阵列，时钟信号发生器，被配置为从存储器件的外部接收外部时钟信号并输出​​内部时钟信号;以及数据输出单元，被配置为从存储器单元接收内部数据信号 阵列并响应于内部时钟信号输出读取数据信号。 半导体存储器件还包括读取数据选通单元，其被配置为基于内部时钟信号的周期时间，输出具有n倍（n是等于或大于2的整数）的周期时间的读取数据选通信号 内部时钟信号。

公开(公告)号：US20100177576A1

公开(公告)日：2010-07-15

申请号：US12686561

申请日：2010-01-13

申请人： Chi-Sung Oh ,  Jung-Bae Lee ,  Dong-Hyuk Lee

发明人： Chi-Sung Oh ,  Jung-Bae Lee ,  Dong-Hyuk Lee

IPC分类号： G11C7/08

CPC分类号： G11C7/065 ,  G11C5/025 ,  G11C7/08 ,  G11C11/4091

摘要： A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense amplifier driving signal driver includes a first driving signal driver configured to drive via a transmission line the sense amplifier driving signal in response to a first sense amplifier control signal, and a second driving signal driver configured to drive via the transmission line the sense amplifier driving signal in response to a second sense amplifier control signal. The controller activates the first sense amplifier control signal in response to an active command, and toggles the second sense amplifier control signal while the first sense amplifier control signal is activated.

摘要翻译： 半导体存储器件包括读出放大器，读出放大器驱动信号驱动器和控制器。 读出放大器被配置为响应于读出放大器驱动信号来检测和放大位线的信号和互补位线的信号。 读出放大器驱动信号驱动器包括：第一驱动信号驱动器，被配置为响应于第一读出放大器控制信号经由传输线驱动读出放大器驱动信号;以及第二驱动信号驱动器，被配置为通过传输线驱动读出放大器 响应于第二读出放大器控制信号的驱动信号。 控制器响应于有效命令激活第一读出放大器控制信号，并且在第一读出放大器控制信号被激活时切换第二读出放大器控制信号。

公开(公告)号：US07577760B2

公开(公告)日：2009-08-18

申请号：US11267669

申请日：2005-11-04

申请人： Jung-Bae Lee

发明人： Jung-Bae Lee

IPC分类号： G06F3/00 ,  G06F13/00 ,  G11C5/06 ,  G11C7/00

CPC分类号： G06F13/1684

摘要： A memory system includes a plurality of memory devices arranged in sets on at least one memory module, each set including at least one memory device. In some embodiments, the system further includes respective dedicated serial data and control busses configured to couple respective ones of the memory device sets to a memory controller external to the at least one memory module. The dedicated serial data and control busses may be configured to provide unbuffered access to the individual memory devices from the memory controller. In other embodiments, dedicated data busses are provided to an external control buffer and dedicated control busses are provided to a control buffer in the module.

摘要翻译： 存储器系统包括在至少一个存储器模块上以组合排列的多个存储器件，每个存储器器件包括至少一个存储器件。 在一些实施例中，系统进一步包括各自的专用串行数据和控制总线，其被配置为将存储器设备组中的相应一个组合耦合到至少一个存储器模块外部的存储器控​​制器。 专用串行数据和控制总线可以被配置为从存储器控制器提供对各个存储器设备的非缓冲访问。 在其他实施例中，将专用数据总线提供给外部控制缓冲器，并将专用控制总线提供给模块中的控制缓冲器。

公开(公告)号：US20080295605A1

公开(公告)日：2008-12-04

申请号：US12128159

申请日：2008-05-28

申请人： YOUNG CHAN JANG ,  Jung-Bae Lee ,  Yun-Sang Lee

发明人： YOUNG CHAN JANG ,  Jung-Bae Lee ,  Yun-Sang Lee

IPC分类号： G01B7/16

CPC分类号： G01R31/2849 ,  G01R31/2621 ,  G01R31/2642 ,  G11C29/12 ,  G11C29/50

摘要： A stress detection circuit includes a function block and a detection signal generation circuit. The function block outputs a first voltage such that the first voltage is varied depending on an extent that the function block is stressed. The detection signal generation circuit generates a stress detection signal based on the first voltage and a second voltage during a test mode. The stress detection signal represents integration of the function block, and a level of the second voltage corresponds to a level of the first voltage before the function block is stressed.

摘要翻译： 应力检测电路包括功能块和检测信号生成电路。 功能块输出第一电压，使得第一电压根据功能块受应力的程度而变化。 检测信号发生电路在测试模式期间产生基于第一电压和第二电压的应力检测信号。 应力检测信号表示功能块的积分，第二电压的电平对应于在功能块受到应力之前的第一电压的电平。

公开(公告)号：US07245140B2

公开(公告)日：2007-07-17

申请号：US10987706

申请日：2004-11-12

申请人： Jung Sunwoo ,  Jung-Bae Lee

发明人： Jung Sunwoo ,  Jung-Bae Lee

IPC分类号： G01R31/26 ,  G11C7/00

CPC分类号： G01R31/31713 ,  G01R31/31723

摘要： A semiconductor device includes an ODT (on die termination) pin coupled to a tester that applies a tester termination control signal thereon. The semiconductor device also includes a measure path that transmits the tester termination control signal from the ODT pin to an ODT circuit during measurement of a parameter of the semiconductor device. The ODT pin and the measure path advantageously allow for control of the ODT circuit by the tester for more accurate parameter characterization.

摘要翻译： 半导体器件包括耦合到测试器的ODT（管芯端子）引脚上的测试器端接控制信号。 半导体器件还包括测量路径，该测量路径在测量半导体器件的参数期间将测试器终止控制信号从ODT引脚传输到ODT电路。 ODT引脚和测量路径有利地允许由测试仪控制ODT电路以获得更准确的参数表征。