公开(公告)号：US20240020058A1

公开(公告)日：2024-01-18

申请号：US17865157

申请日：2022-07-14

Applicant: XILINX, INC.

Inventor： Ygal ARBEL ,  Martin NEWMAN ,  Arul CHINNAPPAN

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0673

Abstract: A state-of-the-art memory controller and methods for using the same are disclosed. The memory controller is intended for use with dynamic random-access memory (DRAM) circuitry. In one example, a memory controller includes a reordering preprocessor circuitry coupled to a reordering scheduler circuitry. The reordering scheduler circuitry is configured to control a reordering scheduler queue, and is coupled to DRAM circuitry. The reordering preprocessor circuitry is configured to control a preprocessor queue and reorder transactions in the preprocessor queue so as to increase the DRAM circuitry performance.

公开(公告)号：US20240291635A1

公开(公告)日：2024-08-29

申请号：US18113588

申请日：2023-02-23

Applicant: XILINX, INC.

Inventor： Abbas MORSHED ,  Ygal ARBEL ,  Balakrishna JAYADEV ,  Eun Mi KIM

IPC: H04L9/08 ,  G06F21/60

CPC classification number: H04L9/0825 ,  G06F21/602 ,  H04L9/0894

Abstract: Examples herein describe techniques for method of accessing encrypted data. The techniques include receiving, via a memory controller, a first memory request to a first memory region, where the first memory region is encrypted based on a first key, and incrementing, based on the first memory request, a first counter associated with the first key. The techniques further include, in response to determining that the first counter exceeds a first threshold, initiating a key rolling operation to cause the first memory region to be encrypted based on a second key. The techniques further include tracking an address range of the first memory region that has been encrypted based on the second key, and, in response to determining that an address of a second memory request is outside of the address range, causing the second memory request to be completed based on the first key.

公开(公告)号：US20240176758A1

公开(公告)日：2024-05-30

申请号：US18432847

申请日：2024-02-05

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Ygal ARBEL ,  Sagheer AHMAD

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0016

Abstract: Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.

公开(公告)号：US20240111693A1

公开(公告)日：2024-04-04

申请号：US17957418

申请日：2022-09-30

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Ygal ARBEL ,  Sagheer AHMAD ,  Sarosh I. AZAD ,  Pramod BHARDWAJ ,  Yanran CHEN ,  James MURRAY

IPC: G06F13/16 ,  G06F11/07

CPC classification number: G06F13/1631 ,  G06F11/0772 ,  G06F13/1668

Abstract: Techniques to provide transaction redundancy in an IC include receiving an original memory access request directed to a first memory aperture, constructing a redundant memory access directed to a second memory aperture, and selectively returning a response of the first or second memory aperture to an originator based on contents of the responses. For a write operation, if acknowledgement indicators of the responses indicate success, a response is returned to the originator. For a read operation, if acknowledgement indicators of the responses indicate success and data returned in the response match one another, a response is returned to the originator. If the acknowledgement indicators indicate success, but the data does not match, a retry of the original and redundant read requests is initiated. If any of the acknowledgement indicators do not indicate success, an error is declared. In a mixed-criticality embodiment, the redundant memory access request may be constructed selectively.

公开(公告)号：US20230244628A1

公开(公告)日：2023-08-03

申请号：US17589633

申请日：2022-01-31

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Sagheer AHMAD ,  Ygal ARBEL ,  Millind MITTAL

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F13/42 ,  G06F13/382 ,  G06F13/4063

Abstract: Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface includes circuitry for performing multiple different C2C protocols to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocols. During runtime, the chip then uses the selected C2C protocol to communicate with the other chip in the C2C connection.

公开(公告)号：US20250077116A1

公开(公告)日：2025-03-06

申请号：US18241142

申请日：2023-08-31

Applicant: XILINX, INC.

Inventor： Ygal ARBEL ,  Krishnan SRINIVASAN

IPC: G06F3/06

Abstract: An integrated circuit device includes interconnect circuitry. The interconnect circuitry includes interleaving switch circuitries, network switch circuitries, and crossbar circuitries. The interleaving switch circuitries are coupled to requester devices. A first interleaving switch circuitry includes first ports. The first interleaving switch circuitry receives a first memory command, and outputs the first memory command via first communication lanes connected to a first port based on a memory address of the first memory command. The network switch circuitries are connected to the interleaving switch circuitries. A first network switch circuitry is connected to the first communication lanes and route the first memory command along the first communication lanes based on the memory address. A first crossbar circuitry of the crossbar circuitries receives the first memory command from the first communication lanes, and outputs the first memory command to a first memory device of the memory devices associated with the memory

公开(公告)号：US20240281325A1

公开(公告)日：2024-08-22

申请号：US18111805

申请日：2023-02-20

Applicant: XILINX, INC.

Inventor： Ygal ARBEL ,  Jonathan JASPER ,  Abbas MORSHED

IPC: G06F11/10 ,  G06F12/0871 ,  G06F12/0891

CPC classification number: G06F11/1068 ,  G06F12/0871 ,  G06F12/0891

Abstract: An integrated circuit (IC) device includes processor circuitry configured to output a first memory command having a first memory address, and in-line error correction control (ILECC) circuitry configured to receive the first memory command and output the first memory command to a memory device. The ILECC circuitry includes an error correction code (ECC) cache configured to store a first local ECC associated with the first memory command in a first cache line.

公开(公告)号：US20240143206A1

公开(公告)日：2024-05-02

申请号：US17974084

申请日：2022-10-26

Applicant: XILINX, INC.

Inventor： Ygal ARBEL

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0622 ,  G06F3/0658 ,  G06F3/0679

Abstract: Embodiments herein describe a memory controller that performs in-line data processing (e.g., cryptography and error correction) and efficiently organizes data and associated metadata in memory. The memory controller generates a data block that includes a processed (e.g., encrypted) dataset and associated metadata (e.g., cryptographic metadata and ECC), and stores the data block in a block of memory (i.e., rather than storing the metadata separately), to minimize a number of access operations. The memory controller may access memory in segments (e.g., BL16 operations) that are smaller than the data blocks. For linear accesses, the memory controller may cache a portion of a data block until a subsequent access operation.

公开(公告)号：US20230141709A1

公开(公告)日：2023-05-11

申请号：US17551132

申请日：2021-12-14

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Ygal ARBEL ,  Sagheer AHMAD

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0016

Abstract: Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.

公开(公告)号：US20220337923A1

公开(公告)日：2022-10-20

申请号：US17232207

申请日：2021-04-16

Applicant: XILINX, INC.

Inventor： Aman GUPTA ,  Sagheer AHMAD ,  Ygal ARBEL ,  Abbas MORSHED ,  Eun Mi KIM

IPC: H04Q3/00 ,  G06F13/40 ,  G06F13/16

Abstract: Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.