公开(公告)号：US11860228B2

公开(公告)日：2024-01-02

申请号：US17742363

申请日：2022-05-11

Applicant: XILINX, INC.

Inventor： Albert Shih-Huai Lin ,  Niravkumar Patel ,  Amitava Majumdar ,  Jane Wang Sowards

IPC: G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/318555 ,  G01R31/31727 ,  G01R31/318572

Abstract: An integrated circuit (IC) chip device includes testing interface circuity and testing circuitry to test the operation of the IC chips of the IC chip device. The IC chip device includes a first IC chip that comprises first testing circuitry. The first testing circuitry receives a mode select signal, a clock signal, and encoded signals, and comprises finite state machine (FSM) circuitry, decoder circuitry, and control circuitry. The FSM circuitry determines an instruction based on the mode select signal and the clock signal. The decoder circuitry decodes the encoded signals to generate a decoded signal. The control circuitry generates a control signal from the instruction and the decoded signal. The control signal indicates a test to be performed by the first testing circuitry.

公开(公告)号：US11263377B1

公开(公告)日：2022-03-01

申请号：US17219174

申请日：2021-03-31

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Albert Shih-Huai Lin ,  Partho Tapan Chaudhuri ,  Niravkumar Patel

IPC: G06F30/333 ,  G06F30/3308 ,  G06F30/398 ,  G06F11/00 ,  G01R31/28 ,  H01L25/00 ,  H03K19/00 ,  G06F115/08 ,  G06F11/08

Abstract: A circuit architecture for expanded design for testability functionality is provided that includes an Intellectual Property (IP) core for use with a design for an integrated circuit (IC). The IP core provides an infrastructure harness circuit configured to control expanded design for testability functions available within the IC. An instance of the IP core can be included in a circuit block of the design for the IC. The infrastructure harness circuit can include an outward facing interface configured to connect to circuitry outside of the circuit block and an inward facing interface configured to connect to circuitry within the circuit block. The instance of the IP core can be parameterized to configure the infrastructure harness circuit to control a plurality of functions selected from the expanded design for testability functions based on a user parameterization of the instance of the IP core.

公开(公告)号：US11755804B2

公开(公告)日：2023-09-12

申请号：US17646184

申请日：2021-12-28

Applicant: Xilinx, Inc.

Inventor： Albert Shih-Huai Lin ,  Rambabu Nerukonda ,  Niravkumar Patel ,  Amitava Majumdar

IPC: G06F30/333 ,  G06F30/367 ,  G06F30/396 ,  G06F30/398 ,  G06F30/20 ,  G06F11/267 ,  G06F11/27 ,  H01L25/00 ,  H03K19/17732 ,  H03K19/17764 ,  G06F115/08 ,  H01L21/66

CPC classification number: G06F30/333 ,  H03K19/17732 ,  H03K19/17764 ,  G06F11/267 ,  G06F11/27 ,  G06F30/20 ,  G06F30/367 ,  G06F30/396 ,  G06F30/398 ,  G06F2115/08 ,  H01L22/34 ,  H01L25/00

Abstract: An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.

公开(公告)号：US20230205959A1

公开(公告)日：2023-06-29

申请号：US17646184

申请日：2021-12-28

Applicant: Xilinx, Inc.

Inventor： Albert Shih-Huai Lin ,  Rambabu Nerukonda ,  Niravkumar Patel ,  Amitava Majumdar

IPC: G06F30/333

CPC classification number: G06F30/333 ,  G06F2115/08

Abstract: An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.

公开(公告)号：US11500017B1

公开(公告)日：2022-11-15

申请号：US17216516

申请日：2021-03-29

Applicant: XILINX, INC.

Inventor： Albert Shih-Huai Lin ,  Amitava Majumdar

IPC: G01R31/3177 ,  G11C29/32 ,  G01R31/317 ,  G11C7/22 ,  G01R31/28 ,  G06F11/36 ,  G01R31/3185 ,  G01R31/319 ,  G06F11/273 ,  G11C29/12

Abstract: A semiconductor device comprises a plurality of memory elements, test control circuitry, and a testing interface. The test control circuitry is configure to determine that one or more clock signals associated with the memory elements have been stopped and generate a scan clock signal based on the determination that the one or more clock signals have been stopped. The test control circuitry is further configured to communicate the scan clock signal to the memory elements. The testing interface is configured to communicate test data from the memory elements. In one example, the test data is delimited with start and end marker elements. The semiconductor device is mounted to a circuit board and is communicatively coupled to communication pins of the circuit board.

公开(公告)号：US11054461B1

公开(公告)日：2021-07-06

申请号：US16351310

申请日：2019-03-12

Applicant: Xilinx, Inc.

Inventor： Nui Chong ,  Amitava Majumdar ,  Cheang-Whang Chang ,  Henley Liu ,  Myongseob Kim ,  Albert Shih-Huai Lin

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/3177 ,  H01L25/065

Abstract: Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test circuits. Each of the set of pads includes the test data-in pad and the test data-out pad respectively thereof. A test data-output path is coupled to the test data-out pad of a level of the levels.