公开(公告)号：US08987009B1

公开(公告)日：2015-03-24

申请号：US13742010

申请日：2013-01-15

Applicant: Xilinx, Inc.

Inventor： Cinti X. Chen ,  Myongseob Kim ,  Xiao-Yu Li ,  Mohsen H. Mardi

IPC: H01L21/71 ,  H01L21/98 ,  H01L21/673 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L22/26 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/17 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2223/54493 ,  H01L2224/13124 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/17515 ,  H01L2924/01013 ,  H01L2924/14 ,  H01L2924/15311

Abstract: A method for tracking an interposer die of a stacked silicon interconnect technology (SSIT) product includes forming a plurality of dummy components on the interposer die, and modifying one or more of the plurality of dummy components on the interposer die to form a unique identifier for the interposer die. An apparatus for a stacked silicon interconnect technology (SSIT) product includes an interposer die, and a plurality of dummy components at the interposer die. One or more of the plurality of dummy components is modifiable to form a unique identifier for the interposer die.

Abstract translation: 一种用于跟踪堆叠硅互连技术（SSIT）产品的插入器管芯的方法包括在插入器管芯上形成多个虚拟部件，并修改插入器管芯上的多个虚拟部件中的一个或多个，以形成唯一的标识符 内插器死亡。 叠层硅互连技术（SSIT）产品的装置包括插入器裸片和插入器裸片上的多个虚拟部件。 多个虚拟部件中的一个或多个可修改以形成用于插入器裸片的唯一标识符。

公开(公告)号：US20140346651A1

公开(公告)日：2014-11-27

申请号：US13899129

申请日：2013-05-21

Applicant: Xilinx, Inc.

Inventor： Qi Xiang ,  Xiao-Yu Li ,  Cinti X. Chen ,  Glenn O'Rourke

IPC: H01L23/60 ,  H01L21/82

CPC classification number: H01L23/60 ,  H01L21/82 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/072 ,  H01L25/18 ,  H01L2924/181 ,  H01L2924/00

Abstract: An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures are to protect at least one integrated circuit die to be coupled to the interposer to provide a stacked die. The plurality of conductors include a plurality of through-substrate vias.

Abstract translation: 公开了一般涉及插入件的装置。 在这种装置中，插入器具有多个导体和多个电荷吸引结构。 多个电荷吸引结构是保护至少一个集成电路管芯，以耦合到插入器以提供堆叠的管芯。 多个导体包括多个贯通基板通路。

公开(公告)号：US11762958B1

公开(公告)日：2023-09-19

申请号：US16591179

申请日：2019-10-02

Applicant: XILINX, INC.

Inventor： Ran Zhou ,  Cinti X. Chen ,  Xiao-Yu Li

IPC: G06F9/44 ,  G06N20/00 ,  G01R31/28 ,  G06F30/34 ,  G06F18/20

CPC classification number: G06F18/295 ,  G01R31/2831 ,  G06F30/34 ,  G06N20/00

Abstract: Examples described herein provide for determining a recipe for identifying from which buckets integrated circuit chips are taken to form units of a multi-chip apparatus. In an example, a method uses a processor-based system and uses a Markov Decision Process. Buckets are defined based on respective characteristics of manufactured chips. Each of the manufactured chips is binned into a respective one of the buckets based on the characteristic of the respective manufactured chip. A recipe for identifying from which of the buckets to take one or more of the manufactured chips to incorporate into respective ones of the units of the multi-chip apparatus is generated.

公开(公告)号：US09236367B1

公开(公告)日：2016-01-12

申请号：US14625145

申请日：2015-02-18

Applicant: Xilinx, Inc.

Inventor： Cinti X. Chen ,  Myongseob Kim ,  Xiao-Yu Li ,  Mohsen H. Mardi

IPC: H01L27/12 ,  H01L25/00 ,  H01L23/544 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L22/26 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/17 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2223/54493 ,  H01L2224/13124 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/17515 ,  H01L2924/01013 ,  H01L2924/14 ,  H01L2924/15311

Abstract: An apparatus for a stacked silicon interconnect technology (SSIT) product comprises an interposer die, a plurality of integrated circuit dies, a plurality of active components forming an active connection between the integrated circuit dies and the interposer die, and a plurality of dummy components at the interposer die, the dummy components not forming an active connection between the integrated circuit dies and the interposer die. At least a subset of the dummy components forms a pattern, and the pattern comprises an identifier for the interposer die.

Abstract translation: 一种用于叠层硅互连技术（SSIT）产品的装置，包括插入器管芯，多个集成电路管芯，在集成电路管芯和内插管芯之间形成有源连接的多个有源部件，以及多个虚设部件 插入器裸片，虚设部件不形成集成电路管芯和内插器管芯之间的有源连接。 虚拟部件的至少一个子集形成图案，并且图案包括插入器裸片的标识符。

公开(公告)号：US09214433B2

公开(公告)日：2015-12-15

申请号：US13899129

申请日：2013-05-21

Applicant: Xilinx, Inc.

Inventor： Qi Xiang ,  Xiao-Yu Li ,  Cinti X. Chen ,  Glenn O'Rourke

IPC: H01L23/552 ,  H01L23/60 ,  H01L21/82 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/60 ,  H01L21/82 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/072 ,  H01L25/18 ,  H01L2924/181 ,  H01L2924/00

Abstract: An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures are to protect at least one integrated circuit die to be coupled to the interposer to provide a stacked die. The plurality of conductors include a plurality of through-substrate vias.

Abstract translation: 公开了一般涉及插入件的装置。 在这种装置中，插入器具有多个导体和多个电荷吸引结构。 多个电荷吸引结构是保护至少一个集成电路管芯，以耦合到插入器以提供堆叠的管芯。 多个导体包括多个贯通基板通路。