公开(公告)号：US10823759B2

公开(公告)日：2020-11-03

申请号：US16180995

申请日：2018-11-05

Applicant: Xilinx, Inc.

Inventor： Lik Huay Lim ,  Andy Widjaja ,  King Yon Lew ,  Mohsen H. Mardi ,  Xuejing Che

IPC: G01R1/06 ,  G01R1/067 ,  G01R1/073

Abstract: A test system for testing a wafer for integrated circuit devices is described. The test system comprises a first plurality of test probes adapted to make electrical contacts to first corresponding contacts of a wafer tested by the test system; a second plurality of test probes adapted to make electrical contacts to second corresponding contacts on a perimeter region of a portion of the wafer tested by the test system; and a control circuit coupled to the first plurality of test probes and the second plurality of test probes; wherein the control circuit determines whether the second plurality of test probes has a proper contact with the wafer based upon signals received by the second plurality of test probes. A method of testing a wafer for an integrated circuit is also described.

公开(公告)号：US10527670B2

公开(公告)日：2020-01-07

申请号：US15471390

申请日：2017-03-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Ivor G. Barber ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Tien-Yu Lee ,  Henley Liu ,  David M. Mahoney ,  Mohsen H. Mardi

IPC: G01R31/28

Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

公开(公告)号：US10520544B2

公开(公告)日：2019-12-31

申请号：US15250390

申请日：2016-08-29

Applicant: Xilinx, Inc.

Inventor： Mohsen H. Mardi

IPC: G01R31/28 ,  G01R31/26 ,  G01R31/02

Abstract: A chip package assembly testing system and method for testing a chip package assembly are provided herein. In one example, an IC test system is provide that includes a robot, an input queuing station, an output queuing station, and a test station. The test station includes a first and second test interfaces. The first test interface is configurable to receive and communicatively connect with a first chip package assembly having one arrangement of solder ball connections. The second test interface is configurable to receive and communicatively connect with a second chip package assembly having a different arrangement of solder ball connections. The test station also includes a first test processor configured to test the chip package assembly connected through the first interface utilizing a predetermined first test routine and a second test processor configured to test the chip package assembly connected through the second interface utilizing a predetermined second test routine.

公开(公告)号：US20180059174A1

公开(公告)日：2018-03-01

申请号：US15250390

申请日：2016-08-29

Applicant: Xilinx, Inc.

Inventor： Mohsen H. Mardi

IPC: G01R31/28

CPC classification number: G01R31/2875 ,  G01R31/2868 ,  G01R31/2874 ,  G01R31/2877 ,  G01R31/2893

Abstract: A chip package assembly testing system and method for testing a chip package assembly are provided herein. In one example, an IC test system is provide that includes a robot, an input queuing station, an output queuing station, and a test station. The test station includes a first and second test interfaces. The first test interface is configurable to receive and communicatively connect with a first chip package assembly having one arrangement of solder ball connections. The second test interface is configurable to receive and communicatively connect with a second chip package assembly having a different arrangement of solder ball connections. The test station also includes a first test processor configured to test the chip package assembly connected through the first interface utilizing a predetermined first test routine and a second test processor configured to test the chip package assembly connected through the second interface utilizing a predetermined second test routine.

公开(公告)号：US09236367B1

公开(公告)日：2016-01-12

申请号：US14625145

申请日：2015-02-18

Applicant: Xilinx, Inc.

Inventor： Cinti X. Chen ,  Myongseob Kim ,  Xiao-Yu Li ,  Mohsen H. Mardi

IPC: H01L27/12 ,  H01L25/00 ,  H01L23/544 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L22/26 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/17 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2223/54493 ,  H01L2224/13124 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/17515 ,  H01L2924/01013 ,  H01L2924/14 ,  H01L2924/15311

Abstract: An apparatus for a stacked silicon interconnect technology (SSIT) product comprises an interposer die, a plurality of integrated circuit dies, a plurality of active components forming an active connection between the integrated circuit dies and the interposer die, and a plurality of dummy components at the interposer die, the dummy components not forming an active connection between the integrated circuit dies and the interposer die. At least a subset of the dummy components forms a pattern, and the pattern comprises an identifier for the interposer die.

Abstract translation: 一种用于叠层硅互连技术（SSIT）产品的装置，包括插入器管芯，多个集成电路管芯，在集成电路管芯和内插管芯之间形成有源连接的多个有源部件，以及多个虚设部件 插入器裸片，虚设部件不形成集成电路管芯和内插器管芯之间的有源连接。 虚拟部件的至少一个子集形成图案，并且图案包括插入器裸片的标识符。

公开(公告)号：US10539610B2

公开(公告)日：2020-01-21

申请号：US15802253

申请日：2017-11-02

Applicant: Xilinx, Inc.

Inventor： Mohsen H. Mardi ,  David M. Mahoney

IPC: G01R31/00 ,  G01R31/28 ,  G01R31/04

Abstract: An integrated chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an integrated circuit chip package test system includes a socket and a workpress. The socket is configured to receive a chip package assembly for testing in the test system. The workpress is positioned over the socket and has a bottom surface that is dynamically conformable to a multi-planar top surface topography of the chip package assembly.

公开(公告)号：US10096502B2

公开(公告)日：2018-10-09

申请号：US15360187

申请日：2016-11-23

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Mohsen H. Mardi ,  Tien-Yu Lee ,  Ivor G. Barber ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

IPC: B23P21/00 ,  H01L21/673 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56

Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.

公开(公告)号：US20180284187A1

公开(公告)日：2018-10-04

申请号：US15471390

申请日：2017-03-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Ivor G. Barber ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Tien-Yu Lee ,  Henley Liu ,  David M. Mahoney ,  Mohsen H. Mardi

IPC: G01R31/28

CPC classification number: G01R31/2891 ,  G01R31/2889

Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

公开(公告)号：US20180144963A1

公开(公告)日：2018-05-24

申请号：US15360187

申请日：2016-11-23

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Mohsen H. Mardi ,  Tien-Yu Lee ,  Ivor G. Barber ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

IPC: H01L21/673 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/67333 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/67109 ,  H01L23/3185 ,  H01L23/3675 ,  H01L24/16 ,  H01L2224/16227

Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.

公开(公告)号：US12048083B2

公开(公告)日：2024-07-23

申请号：US17457595

申请日：2021-12-03

Applicant: XILINX, INC.

Inventor： Mohsen H. Mardi

IPC: H05K1/02

CPC classification number: H05K1/0203

Abstract: Micro devices having enhanced through heat transfer utilizing plungers extending from a heat spreader are provided. In one example, a micro device is provided that includes a plunger retaining block, a plurality of plungers, a mounting substrate and an integrated circuit (IC) die. The plunger retaining block includes a top surface and a bottom surface. The plurality of plungers extend from the bottom surface of the plunger retaining block with at least some of the plurality of plungers contacting the IC die. The IC die is disposed between the plunger retaining block and the mounting substrate, and coupled to the mounting substrate.