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    Circuit for and method of enabling the selection of a circuit
    1.
    发明授权
    Circuit for and method of enabling the selection of a circuit 有权

    公开(公告)号：US10033388B1

    公开(公告)日：2018-07-24

    申请号：US15465402

    申请日：2017-03-21

    Applicant: Xilinx, Inc.

    Inventor： Mini Rawat ,  Pierre Maillard ,  Michael J. Hart

    IPC: H03K19/177 ,  H03K19/00

    Abstract: An integrated circuit enables the selection of a circuit. According to one implementation, a plurality of redundant circuits provide a predetermined function and a voltage sensor may be coupled to receive a reference voltage. A selection circuit may be coupled to the voltage sensor and the reference voltage, wherein the selection circuit selects one of the plurality of redundant circuits to be implemented in the integrated circuit based upon a detected voltage of the reference voltage of the reference voltage.

    Single-event upset mitigation in circuit design for programmable integrated circuits
    2.
    发明授权
    Single-event upset mitigation in circuit design for programmable integrated circuits 有权
    用于可编程集成电路的电路设计中的单事件缓解

    公开(公告)号：US09183338B1

    公开(公告)日：2015-11-10

    申请号：US14487286

    申请日：2014-09-16

    Applicant: Xilinx, Inc.

    Inventor： Praful Jain ,  Pierre Maillard

    IPC: G06F17/50

    CPC classification number: G06F17/5054 ,  G06F17/505

    Abstract: In an example, a method of implementing a circuit design for a programmable integrated circuit (IC) begins by identifying combinatorial logic functions of the circuit design. The method maps, according to a first constraint, a first threshold percentage of the combinatorial logic functions onto a first type of lookup tables (LUTs) of the programmable IC in favor of second type of LUTs of the programmable IC, the second type of LUTs being more susceptible to single event upsets than the first type of LUTs. The method generates a first physical implementation of the circuit design for the programmable IC based on the mapping.

    Abstract translation: 在一个示例中，实现可编程集成电路（IC）的电路设计的方法开始于识别电路设计的组合逻辑功能。 该方法根据第一约束将组合逻辑功能的第一阈值百分比映射到可编程IC的第一类型的查找表（LUT），有利于可编程IC的第二类型的LUT，第二类型的LUT 比第一类型的LUT更容易受到单事件的影响。 该方法基于映射生成可编程IC的电路设计的第一个物理实现。

    Single event latch-up (SEL) mitigation detect and mitigation
    3.
    发明授权
    Single event latch-up (SEL) mitigation detect and mitigation 有权

    公开(公告)号：US10958067B2

    公开(公告)日：2021-03-23

    申请号：US16136104

    申请日：2018-09-19

    Applicant: Xilinx, Inc.

    Inventor： Pierre Maillard ,  Yanran Chen ,  Michael J. Hart

    IPC: H02H9/04 ,  H03K17/693 ,  H02H5/00

    Abstract: An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contact pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.

    Single event latch-up (SEL) mitigation techniques
    7.
    发明授权
    Single event latch-up (SEL) mitigation techniques 有权

    公开(公告)号：US10861848B2

    公开(公告)日：2020-12-08

    申请号：US16110894

    申请日：2018-08-23

    Applicant: Xilinx, Inc.

    Inventor： Michael J. Hart ,  James Karp ,  Mohammed Fakhruddin ,  Pierre Maillard

    IPC: H01L27/06 ,  H01L27/02 ,  H01L49/02 ,  H01L29/73 ,  H01L29/78

    Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

    Single event upset (SEU) mitigation for FinFET technology using fin topology
    8.
    发明授权
    Single event upset (SEU) mitigation for FinFET technology using fin topology 有权

    公开(公告)号：US10366999B2

    公开(公告)日：2019-07-30

    申请号：US15087947

    申请日：2016-03-31

    Applicant: Xilinx, Inc.

    Inventor： Pierre Maillard

    IPC: H01L27/11 ,  H01L29/08 ,  H01L29/78 ,  H01L27/088 ,  H01L27/092

    Abstract: Front end circuits that include a FinFET transistor are described herein. In one example, the front end circuit has a FinFET transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. At least one of the source and drain fins have a height (HTOT) and a width W. The height (HTOT) is greater than an optimal height (HOPT), wherein the height HOPT is a height that would optimize speed of a FinFET transistor having the width W.

    SINGLE EVENT LATCH-UP (SEL) MITIGATION DETECT AND MITIGATION
    9.
    发明申请
    SINGLE EVENT LATCH-UP (SEL) MITIGATION DETECT AND MITIGATION 审中-公开

    公开(公告)号：US20200091713A1

    公开(公告)日：2020-03-19

    申请号：US16136104

    申请日：2018-09-19

    Applicant: Xilinx, Inc.

    Inventor： Pierre Maillard ,  Yanran Chen ,  Michael J. Hart

    IPC: H02H9/04 ,  H03K17/693

    Abstract: An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contract pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.

    Selection of logic paths for redundancy
    10.
    发明授权
    Selection of logic paths for redundancy 有权
    选择冗余的逻辑路径

    公开(公告)号：US09484919B1

    公开(公告)日：2016-11-01

    申请号：US14266547

    申请日：2014-04-30

    Applicant: Xilinx, Inc.

    Inventor： Praful Jain ,  Pierre Maillard ,  James Karp ,  Michael J. Hart

    IPC: H03K19/003

    CPC classification number: H03K19/00392

    Abstract: Approaches are disclosed for processing a circuit design to protect against single event upsets. A logic path of the circuit design is selected for redundancy based on a total of failure rates of circuit elements in the logic path being greater than a product of a target reduction in failure rate of the logic path and a failure rate of a voting circuit. The circuit design is modified to include at least three instances of the logic path coupled in parallel and a voting circuit coupled to receive output signals from the instances of the logic path. The modified circuit design is stored in a memory.

    Abstract translation: 公开了用于处理电路设计以防止单个事件扰乱的方法。 基于逻辑路径中的电路元件的故障率的总和大于逻辑路径的故障率的目标降低与投票电路的故障率的乘积的总和，选择电路设计的逻辑路径用于冗余。 电路设计被修改为包括并联耦合的逻辑路径的至少三个实例和耦合以从逻辑路径的实例接收输出信号的投票电路。 修改后的电路设计存储在存储器中。

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