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    MULTIPLEXER-BASED TERNARY CONTENT ADDRESSABLE MEMORY
    2.
    发明申请
    MULTIPLEXER-BASED TERNARY CONTENT ADDRESSABLE MEMORY 有权
    基于多路复用器的内容可寻址存储器

    公开(公告)号：US20160293255A1

    公开(公告)日：2016-10-06

    申请号：US14675159

    申请日：2015-03-31

    Applicant: XILINX, INC.

    Inventor： Pongstorn Maidee

    IPC: G11C15/04

    CPC classification number: G11C15/04 ,  G11C15/00 ,  G11C15/046

    Abstract: In one example, a ternary content addressable memory (TCAM) includes an input port coupled to receive a W-bit key as input, and an output port coupled to provide a match vector as output, the match vector including at least one bit. The TCAM further includes a memory having memory cells operable to store N*W pairs of bits for N W-bit TCAM words. The memory includes a plurality of memory outputs. The TCAM further includes at least one compare circuit. The at least one compare circuit includes at least one multiplexer each coupled to receive as input a true version and a complement version of a bit of the W-bit key. Each of the at least one multiplexer is controlled by a respective pair of memory outputs of the plurality of memory outputs. The at least one compare circuit further includes combinatorial logic coupled to perform at least one logical AND operation based on output of the at least one multiplexer.

    Abstract translation: 在一个示例中，三进制内容可寻址存储器（TCAM）包括耦合以接收作为输入的W位密钥的输入端口和耦合以提供匹配向量作为输出的输出端口，所述匹配向量包括至少一个位。 TCAM还包括存储器，其具有可操作用于存储N个W位TCAM字的N * W比特位的存储器单元。 存储器包括多个存储器输出。 TCAM还包括至少一个比较电路。 所述至少一个比较电路包括至少一个多路复用器，每个多路复用器被耦合以作为输入接收W位密钥的真实版本和补码版本。 所述至少一个多路复用器中的每一个由所述多个存储器输出的相应的一对存储器输出控制。 所述至少一个比较电路还包括耦合以基于所述至少一个多路复用器的输出执行至少一个逻辑与运算的组合逻辑。

    Active-by-active programmable device
    3.
    再颁专利
    Active-by-active programmable device 有权

    公开(公告)号：USRE50370E1

    公开(公告)日：2025-04-08

    申请号：US17880487

    申请日：2022-08-24

    Applicant: XILINX, INC.

    Inventor： Alireza Kaviani ,  Pongstorn Maidee ,  Ivo Bolsens

    IPC: G06F13/36 ,  G06F13/00 ,  G06F13/362 ,  G06F13/40

    Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.

    Acceleration-ready program development and deployment for computer systems and hardware acceleration
    4.
    发明授权
    Acceleration-ready program development and deployment for computer systems and hardware acceleration 有权

    公开(公告)号：US11886854B1

    公开(公告)日：2024-01-30

    申请号：US17363920

    申请日：2021-06-30

    Applicant: Xilinx, Inc.

    Inventor： Pongstorn Maidee

    IPC: G06F8/61 ,  G06F9/448 ,  G06F9/445

    CPC classification number: G06F8/61 ,  G06F9/4494 ,  G06F9/44521 ,  G06F9/44536

    Abstract: Acceleration-ready program development includes providing a software library having a plurality of functions having compute identifiers. The software library is associated with a hardware library including one or more hardware accelerated functions. The hardware accelerated functions are associated with the compute identifiers. Each hardware accelerated function is a functional equivalent of a function of the software library having the same compute identifier. A hybrid executor layer is provided that, when executed by a data processing system with an acceleration-ready computer program built using the software library, is configured to initiate execution of a selected function of the acceleration-ready computer program using a processor of the data processing system or invoke a hardware accelerated function having a compute identifier matching the compute identifier of the selected function based on comparing acceleration criteria with acceleration rules.

    Active-by-active programmable device
    5.
    再颁专利
    Active-by-active programmable device 有权

    公开(公告)号：USRE49163E1

    公开(公告)日：2022-08-09

    申请号：US16891972

    申请日：2020-06-18

    Applicant: XILINX, INC.

    Inventor： Alireza S. Kaviani ,  Pongstorn Maidee ,  Ivo Bolsens

    IPC: G06F13/36 ,  G06F13/40 ,  G06F13/362 ,  G06F13/00

    Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.

    Method and apparatus for inter-die data transfer
    6.
    发明授权
    Method and apparatus for inter-die data transfer 有权

    公开(公告)号：US10534729B1

    公开(公告)日：2020-01-14

    申请号：US15979044

    申请日：2018-05-14

    Applicant: Xilinx, Inc.

    Inventor： Pongstorn Maidee ,  Theepan Moorthy

    IPC: G06F13/00 ,  G06F13/16 ,  G06F1/04 ,  G06F13/42

    Abstract: An inter-die data transfer system includes a receiver circuit in a receiver die coupled to a sender circuit in a sender die through a bus. The receiver circuit includes a safe sample selection circuit and a latency adjustment circuit. The safe sample selection circuit receives from the sender circuit a plurality of training data signals, and determines a safe sample selection signal for a first bit of the bus. The latency adjustment circuit determines a latency adjustment selection signal for the first bit of the bus. A user data safe sample is selected using the safe sample selection signal from a plurality of user data samples associated with a first user data input signal associated with the first bit of the bus. Latency adjustment is performed to the user data safe sample to generate a first user data output signal using the latency adjustment selection signal.

    Packet-based and time-multiplexed network-on-chip
    7.
    发明授权
    Packet-based and time-multiplexed network-on-chip 有权

    公开(公告)号：US11496418B1

    公开(公告)日：2022-11-08

    申请号：US17002648

    申请日：2020-08-25

    Applicant: Xilinx, Inc.

    Inventor： Zachary Blair ,  Pongstorn Maidee ,  Alireza S. Kaviani

    IPC: H04L49/109 ,  H04L49/15 ,  H04J3/06

    Abstract: An integrated circuit can include a Network-on-Chip (NoC) having a router network with first and second shared physical channels. The NoC includes one or more master bridge circuits (MBCs) coupled to the router network, where each MBC provides a packet-based interface to a master client circuit coupled thereto for initiating transactions over the router network. Each MBC sends and receives data for the transactions over the router network as flits of packets according to a schedule. The NoC includes one or more slave bridge circuits (SBCs) coupled to the router network, where each SBC provides a packet-based interface to a slave client circuit coupled thereto to for responding to the transactions over the router network. Each SBC sends and receives the flits over the router network according to the schedule. The flits sent from different client circuits are interleaved using time-multiplexing on the first and second shared physical channels.

    Multiplexer-based ternary content addressable memory
    10.
    发明授权
    Multiplexer-based ternary content addressable memory 有权

    公开(公告)号：US09653165B2

    公开(公告)日：2017-05-16

    申请号：US14675159

    申请日：2015-03-31

    Applicant: Xilinx, Inc.

    Inventor： Pongstorn Maidee

    IPC: G11C15/00 ,  G11C15/04

    CPC classification number: G11C15/04 ,  G11C15/00 ,  G11C15/046

    Abstract: In one example, a ternary content addressable memory (TCAM) includes an input port coupled to receive a W-bit key as input, and an output port coupled to provide a match vector as output, the match vector including at least one bit. The TCAM further includes a memory having memory cells operable to store N*W pairs of bits for N W-bit TCAM words. The memory includes a plurality of memory outputs. The TCAM further includes at least one compare circuit. The at least one compare circuit includes at least one multiplexer each coupled to receive as input a true version and a complement version of a bit of the W-bit key. Each of the at least one multiplexer is controlled by a respective pair of memory outputs of the plurality of memory outputs. The at least one compare circuit further includes combinatorial logic coupled to perform at least one logical AND operation based on output of the at least one multiplexer.

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