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    Data-driven pattern matching in synthesis of circuit designs
    1.
    发明授权
    Data-driven pattern matching in synthesis of circuit designs 有权
    电路设计合成中的数据驱动模式匹配

    公开(公告)号：US08938700B1

    公开(公告)日：2015-01-20

    申请号：US13762251

    申请日：2013-02-07

    Applicant: Xilinx, Inc.

    Inventor： Elliott Delaye ,  Alireza S. Kaviani ,  Ashish Sirasao ,  Yinyi Wang

    IPC: G06F17/50

    CPC classification number: G06F17/505

    Abstract: Data-driven processing of a circuit design includes converting each pattern of one or more input patterns from a first format into a second format. Each pattern identifies one or more inputs and one or more outputs and specifies each function that generates each of the one or more outputs from the one or more inputs. Each pattern of the second format is stored in a database. An input circuit design is searched for circuit design elements that match patterns in the database. Data indicative of each pattern in the database that matches a circuit design element is output.

    Abstract translation: 电路设计的数据驱动处理包括将一个或多个输入模式的每个模式从第一格式转换为第二格式。 每个模式识别一个或多个输入和一个或多个输出，并且指定从一个或多个输入产生一个或多个输出中的每一个的每个功能。 第二格式的每个模式都存储在数据库中。 搜索与数据库中的模式匹配的电路设计元素的输入电路设计。 输出指示数据库中与电路设计元素匹配的每个模式的数据。

    Active-by-active programmable device
    2.
    再颁专利
    Active-by-active programmable device 有权

    公开(公告)号：USRE49163E1

    公开(公告)日：2022-08-09

    申请号：US16891972

    申请日：2020-06-18

    Applicant: XILINX, INC.

    Inventor： Alireza S. Kaviani ,  Pongstorn Maidee ,  Ivo Bolsens

    IPC: G06F13/36 ,  G06F13/40 ,  G06F13/362 ,  G06F13/00

    Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.

    Folding duplicate instances of modules in a circuit design
    3.
    发明授权
    Folding duplicate instances of modules in a circuit design 有权

    公开(公告)号：US09875330B2

    公开(公告)日：2018-01-23

    申请号：US14960176

    申请日：2015-12-04

    Applicant: Xilinx, Inc.

    Inventor： Ilya K. Ganusov ,  Henri Fraisse ,  Ashish Sirasao ,  Alireza S. Kaviani

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5054

    Abstract: Disclosed approaches for processing a circuit design include identifying duplicate instances of a module in a representation of the circuit design. A processor circuit performs folding operations for at least one pair of the duplicate instances of the module. One instance of the duplicates is removed from the circuit design, and a multiplexer is inserted. The multiplexer receives and selects one of the input signals to the duplicate instances and provides the selected input signal to the remaining instance. For each flip-flop in the remaining instance, a pipelined flip-flop is inserted. Connections to a first clock signal in the remaining instance are replaced with connections to a second clock signal having twice the frequency of the first clock signal. An alignment circuit is inserted to receive the output signal from the first instance and provide concurrent first and second output signals.

    Active-by-active programmable device
    4.
    发明授权
    Active-by-active programmable device 有权

    公开(公告)号：US10002100B2

    公开(公告)日：2018-06-19

    申请号：US15013696

    申请日：2016-02-02

    Applicant: Xilinx, Inc.

    Inventor： Alireza S. Kaviani ,  Pongstorn Maidee ,  Ivo Bolsens

    IPC: G06F13/36 ,  G06F13/362 ,  G06F13/00 ,  G06F13/40

    CPC classification number: G06F13/4068 ,  G06F13/362 ,  G06F13/4031

    Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.

    ACTIVE-BY-ACTIVE PROGRAMMABLE DEVICE
    5.
    发明申请
    ACTIVE-BY-ACTIVE PROGRAMMABLE DEVICE 有权

    公开(公告)号：US20170220509A1

    公开(公告)日：2017-08-03

    申请号：US15013696

    申请日：2016-02-02

    Applicant: Xilinx, Inc.

    Inventor： Alireza S. Kaviani ,  Pongstorn Maidee ,  Ivo Bolsens

    IPC: G06F13/40 ,  G06F13/362

    CPC classification number: G06F13/4068 ,  G06F13/362 ,  G06F13/4031

    Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.

    Packet-based and time-multiplexed network-on-chip
    6.
    发明授权
    Packet-based and time-multiplexed network-on-chip 有权

    公开(公告)号：US11496418B1

    公开(公告)日：2022-11-08

    申请号：US17002648

    申请日：2020-08-25

    Applicant: Xilinx, Inc.

    Inventor： Zachary Blair ,  Pongstorn Maidee ,  Alireza S. Kaviani

    IPC: H04L49/109 ,  H04L49/15 ,  H04J3/06

    Abstract: An integrated circuit can include a Network-on-Chip (NoC) having a router network with first and second shared physical channels. The NoC includes one or more master bridge circuits (MBCs) coupled to the router network, where each MBC provides a packet-based interface to a master client circuit coupled thereto for initiating transactions over the router network. Each MBC sends and receives data for the transactions over the router network as flits of packets according to a schedule. The NoC includes one or more slave bridge circuits (SBCs) coupled to the router network, where each SBC provides a packet-based interface to a slave client circuit coupled thereto to for responding to the transactions over the router network. Each SBC sends and receives the flits over the router network according to the schedule. The flits sent from different client circuits are interleaved using time-multiplexing on the first and second shared physical channels.

    FOLDING DUPLICATE INSTANCES OF MODULES IN A CIRCUIT DESIGN
    9.
    发明申请
    FOLDING DUPLICATE INSTANCES OF MODULES IN A CIRCUIT DESIGN 有权

    公开(公告)号：US20170161419A1

    公开(公告)日：2017-06-08

    申请号：US14960176

    申请日：2015-12-04

    Applicant: Xilinx, Inc.

    Inventor： Ilya K. Ganusov ,  Henri Fraisse ,  Ashish Sirasao ,  Alireza S. Kaviani

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5054

    Abstract: Disclosed approaches for processing a circuit design include identifying duplicate instances of a module in a representation of the circuit design. A processor circuit performs folding operations for at least one pair of the duplicate instances of the module. One instance of the duplicates is removed from the circuit design, and a multiplexer is inserted. The multiplexer receives and selects one of the input signals to the duplicate instances and provides the selected input signal to the remaining instance. For each flip-flop in the remaining instance, a pipelined flip-flop is inserted. Connections to a first clock signal in the remaining instance are replaced with connections to a second clock signal having twice the frequency of the first clock signal. An alignment circuit is inserted to receive the output signal from the first instance and provide concurrent first and second output signals.

    Lut cascading circuit
    10.
    发明授权
    Lut cascading circuit 有权

    公开(公告)号：US09602108B1

    公开(公告)日：2017-03-21

    申请号：US14852164

    申请日：2015-09-11

    Applicant: Xilinx, Inc.

    Inventor： Brian C. Gaide ,  Steven P. Young ,  Alireza S. Kaviani

    IPC: H03K19/173 ,  H03K19/177 ,  H03K19/00

    CPC classification number: H03K19/17728 ,  H03K19/0008 ,  H03K19/17744 ,  H03K19/1776

    Abstract: In an example, a LUT for a programmable integrated circuit (IC) includes a plurality of input terminals, and a cascading input coupled to at least one other LUT in the programmable IC. The LUT further includes LUT logic having a plurality of LUTs each coupled to a common set of the input terminals. The LUT further includes a plurality of multiplexers having inputs coupled to outputs of the plurality of LUTs, and an output multiplexer having inputs coupled to outputs of the plurality of multiplexers. The LUT further includes a plurality of cascading multiplexers each having an output coupled to a control input of a respective one of the plurality of multiplexers, each of the plurality of cascading multiplexers comprising a plurality of inputs, at least one of the plurality of inputs coupled to the cascading input.

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