公开(公告)号：US10713403B1

公开(公告)日：2020-07-14

申请号：US16374494

申请日：2019-04-03

Applicant: Xilinx, Inc.

Inventor： Shreegopal S. Agrawal ,  Jaipal R. Nareddy ,  Suman Kumar Timmireddy ,  Benjamin D. Curry ,  Siddharth Rele ,  Sozon Panou

IPC: G06F30/30 ,  G06F30/20 ,  G06F30/31 ,  G06F30/327 ,  G06F30/323

Abstract: Apparatus and associated methods relate to controlling synthesis of an electronic design by tagging an intellectual property (IP) parameter such that changes to the tagged design parameter do not result in the entire electronic design being re-synthesized. In an illustrative example, a circuit may contain a number of hard blocks, which may be configured using an HDL design tool. Whenever an IP parameter of an HDL design is updated, place and route may go out of date, which may require the entire design to be re-synthesized. By tagging certain IP parameters with at least one tag, changes or alterations to these tagged IP parameters will not cause synthesis to occur (for output products associated with the at least one tag). Avoiding re-synthesis may save significant time for designers by performing re-synthesis only when necessary.

公开(公告)号：US11188684B2

公开(公告)日：2021-11-30

申请号：US16686070

申请日：2019-11-15

Applicant: XILINX, INC.

Inventor： Gangadhar Budde ,  Shreegopal S. Agrawal ,  Siddharth Rele ,  Subhojit Deb

IPC: G06F21/76

Abstract: Creation of subsystems for a user design to be implemented in an integrated circuit (IC) includes generating, using computer hardware, a subsystem topology based on user provided subsystem data, wherein the subsystem topology specifies a plurality of subsystems of the user design where each subsystem includes a master circuit, and determining, using the computer hardware, a system management identifier for each master circuit of the subsystem topology. Programming data for programmable protection circuits of the IC can be automatically generated using the computer hardware based on the subsystem topology and system management identifiers. The programmable protection circuits, when programmed with the programming data, form the plurality of subsystems and physically isolate the plurality of subsystems on the integrated circuit from one another.

公开(公告)号：US11029964B1

公开(公告)日：2021-06-08

申请号：US16282216

申请日：2019-02-21

Applicant: Xilinx, Inc.

Inventor： Siddharth Rele ,  Shreegopal S. Agrawal ,  Kaustuv Manji ,  Aditya Chaubal

IPC: G06F9/4401 ,  G06F21/30 ,  G06F15/78

Abstract: Approaches for configuring a system-on-chip (SOC) include generating component images for components of the SOC. A first component image is for a platform management controller, a second component image is for programmable logic, and a third component image is for a processor subsystem. The plurality of component images are assembled into a programmable device image, and the programmable device image is input to the platform management controller. The platform management controller is booted from the first component image, the programmable logic is configured with the second component image by the platform management controller in executing the first component image, and the processor subsystem is configured with the third component image by the platform management controller in executing the first component image.

公开(公告)号：US10437946B1

公开(公告)日：2019-10-08

申请号：US15255013

申请日：2016-09-01

Applicant: Xilinx, Inc.

Inventor： Amit Kasat ,  Shreegopal S. Agrawal ,  Venkat Prasad Aleti

IPC: G06F17/50

Abstract: Using pin planning for core sources includes identifying, using a processor, a first pin configuration and a second pin configuration for a core source of a behavioral description of a circuit design. The second pin configuration is generated by a pin planning operation. The first pin configuration of the core source can be compared with the second pin configuration of the core source using a processor. Responsive to detecting a difference between the first pin configuration and the second pin configuration, the core source can be automatically update, using the processor, based upon the second pin configuration.

公开(公告)号：US20210150072A1

公开(公告)日：2021-05-20

申请号：US16686070

申请日：2019-11-15

Applicant: XILINX, INC.

Inventor： Gangadhar Budde ,  Shreegopal S. Agrawal ,  Siddharth Rele ,  Subhojit Deb

IPC: G06F21/76

Abstract: Creation of subsystems for a user design to be implemented in an integrated circuit (IC) includes generating, using computer hardware, a subsystem topology based on user provided subsystem data, wherein the subsystem topology specifies a plurality of subsystems of the user design where each subsystem includes a master circuit, and determining, using the computer hardware, a system management identifier for each master circuit of the subsystem topology. Programming data for programmable protection circuits of the IC can be automatically generated using the computer hardware based on the subsystem topology and system management identifiers. The programmable protection circuits, when programmed with the programming data, form the plurality of subsystems and physically isolate the plurality of subsystems on the integrated circuit from one another.

公开(公告)号：US10067642B1

公开(公告)日：2018-09-04

申请号：US14639768

申请日：2015-03-05

Applicant: Xilinx, Inc.

Inventor： David Robinson ,  Sumit Nagpal ,  Prashanth Kumar ,  Shreegopal S. Agrawal

IPC: G06F17/30 ,  G06F3/0482 ,  G06F9/38

Abstract: Core processing and parameterization may include detecting, using a processor, a super parameter within a core, and, responsive to the detecting, automatically creating, using the processor, a data structure within a memory element having a hierarchy and having a parameter of the core. The data structure may be set as a value of the super parameter of the core.