公开(公告)号：US11451230B2

公开(公告)日：2022-09-20

申请号：US16857090

申请日：2020-04-23

Applicant: XILINX, INC.

Inventor： Steven P. Young ,  Brian C. Gaide

IPC: H03K19/17748 ,  H03K19/17736 ,  G06F1/10 ,  G06F8/40

Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.

公开(公告)号：US09859896B1

公开(公告)日：2018-01-02

申请号：US14851601

申请日：2015-09-11

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Steven P. Young ,  Eric F. Dellinger

IPC: H03K19/177

CPC classification number: H03K19/17744 ,  H03K19/17728

Abstract: In an example, a programmable integrated circuit (IC) includes external contacts configured to interface with a substrate and a plurality of configurable logic elements (CLEs) distributed across a programmable fabric. The programmable IC further includes interconnect circuits disposed between the plurality of CLEs and the external contacts. A plurality of the interconnect circuits is disposed in the plurality of CLEs.

公开(公告)号：US08773164B1

公开(公告)日：2014-07-08

申请号：US13666271

申请日：2012-11-01

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Steven P. Young

IPC: H03K19/173

CPC classification number: H03K19/1776 ,  H03K19/17736

Abstract: In an apparatus, an interconnect block includes a plurality of configuration memory cells. A plurality of multiplexers is respectively coupled to the configuration memory cells. An acknowledge circuit is coupled to the configuration memory cells. The acknowledge circuit includes a plurality of acknowledge inputs. The configuration memory cells are coupled to selectively set states of the plurality of multiplexers and correspondingly selectively activate inputs of the plurality of acknowledge inputs. A data ready circuit is coupled to at least one multiplexer output of the plurality of multiplexers.

Abstract translation: 在一种装置中，互连块包括多个配置存储单元。 多个复用器分别耦合到配置存储器单元。 确认电路耦合到配置存储器单元。 确认电路包括多个确认输入。 配置存储器单元被耦合以选择性地设置多个多路复用器的状态，并且相应地选择性地激活多个确认输入的输入。 数据就绪电路耦合到多个复用器的至少一个复用器输出端。

公开(公告)号：US11750195B2

公开(公告)日：2023-09-05

申请号：US17876456

申请日：2022-07-28

Applicant: XILINX, INC.

Inventor： Steven P. Young ,  Brian C. Gaide

IPC: H03K19/17748 ,  G06F1/10 ,  G06F8/40 ,  H03K19/17736

CPC classification number: H03K19/17748 ,  G06F1/10 ,  G06F8/40 ,  H03K19/17736

Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.

公开(公告)号：US11239203B2

公开(公告)日：2022-02-01

申请号：US16672077

申请日：2019-11-01

Applicant: XILINX, INC.

Inventor： Brian C. Gaide ,  Steven P. Young

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

Abstract: Examples described herein generally related to multi-chip devices having vertically stacked chips. In an example, a multi-chip device includes a chip stack. The chip stack includes a base chip and a plurality of interchangeable chips. The base chip is directly bonded to a first one of the plurality of interchangeable chips. Each neighboring pair of the plurality of interchangeable chips is directly bonded together in an orientation with a front side of one chip of the respective neighboring pair directly bonded to a backside of the other chip of the respective neighboring pair. Each of the interchangeable chips has a same processing integrated circuit and a same hardware layout. The chip stack can include a distal chip, which can be directly bonded to a second one of the plurality of interchangeable chips.

公开(公告)号：US09602108B1

公开(公告)日：2017-03-21

申请号：US14852164

申请日：2015-09-11

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Steven P. Young ,  Alireza S. Kaviani

IPC: H03K19/173 ,  H03K19/177 ,  H03K19/00

CPC classification number: H03K19/17728 ,  H03K19/0008 ,  H03K19/17744 ,  H03K19/1776

Abstract: In an example, a LUT for a programmable integrated circuit (IC) includes a plurality of input terminals, and a cascading input coupled to at least one other LUT in the programmable IC. The LUT further includes LUT logic having a plurality of LUTs each coupled to a common set of the input terminals. The LUT further includes a plurality of multiplexers having inputs coupled to outputs of the plurality of LUTs, and an output multiplexer having inputs coupled to outputs of the plurality of multiplexers. The LUT further includes a plurality of cascading multiplexers each having an output coupled to a control input of a respective one of the plurality of multiplexers, each of the plurality of cascading multiplexers comprising a plurality of inputs, at least one of the plurality of inputs coupled to the cascading input.

公开(公告)号：US09509307B1

公开(公告)日：2016-11-29

申请号：US14492370

申请日：2014-09-22

Applicant: Xilinx, Inc.

Inventor： Vikram Santurkar ,  Anil Kumar Kandala ,  Santosh Yachareni ,  Shidong Zhou ,  Robert Fu ,  Philip Costello ,  Sandeep Vundavalli ,  Steven P. Young ,  Brian C. Gaide

IPC: H03K19/003 ,  H03K19/173 ,  H03K19/00 ,  G11C7/12

CPC classification number: H03K19/003 ,  G11C5/147 ,  G11C5/148 ,  G11C7/20 ,  G11C11/417 ,  H03K19/0008 ,  H03K19/1737

Abstract: An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.

Abstract translation: 互连多路复用器包括第一多路复用器级的多个CMOS通过门，其耦合以接收由互连多路复用器输出的数据; 输出反相器，其耦合到所述多个CMOS遍栅的输出，其中所述输出反相器的输出是所述互连多路复用器的输出; 以及耦合到所述多个CMOS通孔的多个存储元件; 其中在启动模式期间将多个CMOS通孔的输入拉至公共电位。 还公开了降低集成电路中的争用电流的方法。

公开(公告)号：US08773166B1

公开(公告)日：2014-07-08

申请号：US13666236

申请日：2012-11-01

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Steven P. Young

IPC: H03K19/0175

CPC classification number: H03K19/01759 ,  H03K19/01707

Abstract: An apparatus includes a first output stage and a first input stage of a first single track buffer, as well as a second output stage and a second input stage of a second single track buffer. The second single track buffer is downstream from the first single track buffer. The first output stage and the second input stage are coupled to one another via bidirectional rails. The first output stage and the second input stage in combination provide a first pulse generator.

Abstract translation: 一种装置包括第一单轨道缓冲器的第一输出级和第一输入级，以及第二单轨迹缓冲器的第二输出级和第二输入级。 第二单轨道缓冲器是从第一单轨道缓冲器的下游。 第一输出级和第二输入级通过双向导轨相互耦合。 第一输出级和第二输入级组合提供第一脉冲发生器。

公开(公告)号：US10825772B2

公开(公告)日：2020-11-03

申请号：US16571788

申请日：2019-09-16

Applicant: XILINX, INC.

Inventor： Steven P. Young ,  Brian C. Gaide

IPC: H01L23/538 ,  H01L21/66 ,  H01L25/065

Abstract: Some examples described herein relate to redundancy in a multi-chip stacked device. An example described herein is a multi-chip device. The multi-chip device includes a chip stack including vertically stacked chips. Neighboring pairs of the chips are directly connected together. Each of two or more of the chips includes a processing integrated circuit. The chip stack is configurable to operate a subset of functionality of the processing integrated circuits of the two or more of the chips when any portion of the processing integrated circuits is defective.

公开(公告)号：US11270977B2

公开(公告)日：2022-03-08

申请号：US16679063

申请日：2019-11-08

Applicant: XILINX, INC.

Inventor： Praful Jain ,  Steven P. Young ,  Martin L. Voogel ,  Brian C. Gaide

IPC: H01L25/065 ,  H01L25/00

Abstract: An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.