Three-dimensional memory device with source structure and methods for forming the same

    公开(公告)号:US11805650B2

    公开(公告)日:2023-10-31

    申请号:US17550580

    申请日:2021-12-14

    CPC分类号: H10B43/27 H10B43/10 H10B43/35

    摘要: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes the following operations. First, a slit structure and a support structure are formed in a stack structure having interleaved a plurality of sacrificial material layers and a plurality of insulating material layers, the initial support structure between adjacent slit openings of the slit structure. A source structure is formed to include a source portion in each of the slit openings. A pair of first portions of a connection layer is formed in contact with and conductively connected to the source portion. A second portion of the connection layer is formed in contact with and conductively to the pair of first portions of the connection layer.

    Three-dimensional memory device with source structure and methods for forming the same

    公开(公告)号:US11437398B2

    公开(公告)日:2022-09-06

    申请号:US16863203

    申请日:2020-04-30

    摘要: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack over a substrate, a plurality of channel structures, a source structure, and a support structure. The memory stack includes interleaved a plurality of conductor layers and a plurality of insulating layers. The plurality of channel structures extend vertically in the memory stack. The source structure includes a plurality of source portions and extending in the memory stack. The support structure is between adjacent ones of the source portions and has a plurality of interleaved conductor portions and insulating portions. A top one of the conductor portions is in contact with a top one of the conductor layers. Adjacent ones of the source portions are conductively connected to one another.

    Three-dimensional memory and fabrication method thereof

    公开(公告)号:US12052871B2

    公开(公告)日:2024-07-30

    申请号:US17496031

    申请日:2021-10-07

    IPC分类号: H10B43/27 H10B43/10 H10B43/35

    CPC分类号: H10B43/27 H10B43/10 H10B43/35

    摘要: Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the method for forming the 3D memory device includes forming an alternating dielectric stack on a substrate, and forming channel holes that penetrate the alternating dielectric stack and expose at least a portion of the substrate. The method further includes forming top select gate openings that penetrate vertically an upper portion of the alternating dielectric stack and extend laterally. The method also includes forming slit openings parallel to the top select gate openings, wherein the slit openings penetrate vertically the alternating dielectric stack. The method also includes replacing the alternating dielectric stack with a film stack of alternating conductive and dielectric layers, forming top select gate cuts in the top select gate openings, and forming slit structures in the slit openings.

    Three-dimensional memory device with support structures in gate line slits and methods for forming the same

    公开(公告)号:US11114458B2

    公开(公告)日:2021-09-07

    申请号:US16670594

    申请日:2019-10-31

    摘要: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the 3D memory device includes a memory stack having interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack. The 3D memory device also includes a plurality of channel structures extending vertically through the memory stack into the substrate. The 3D memory device further includes at least one slit structure extending vertically and laterally in the memory stack and dividing a plurality of memory cells into at least one memory block, the at least one slit structure each including a plurality of slit openings and a support structure between adjacent slit openings. The support structure may be in contact with adjacent memory blocks and contacting the substrate.