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公开(公告)号：US07941782B2
公开(公告)日：2011-05-10
申请号：US11943771
申请日：2007-11-21
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G11C5/025 , H01L27/115 , Y10T428/24802
摘要： In a pattern layout which includes a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed parallel to one anther and uniformly arranged with constant width at a constant pitch and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly arranged, and a second device pattern arranged adjacent to the end portion of the non-uniformly repeated pattern group in an arrangement direction thereof and having second lines and second spaces whose widths are larger than the widths of the first lines and first spaces of the non-uniformly repeated pattern group, at least part of the widths of the first lines and the first spaces of the non-uniformly repeated pattern group is made larger than the width of the first line or the width of the first space of the uniformly repeated pattern group.
摘要翻译： 在图案布局中，包括具有均匀重复的图案组的第一装置图案，该第一装置图案具有第一线和平行于一个花柱形成的第一间隔，并且以恒定间距均匀地布置，并且具有第一线和第一线的不均匀重复的图案组 以及与其非排列方向上的非均匀重复图形组的端部相邻排列的第二装置图案，并且具有第二线和第二空间，第二线和第二空间的宽度大于第一线和第一线的宽度 不均匀重复图案组的空间，使不均匀重复图案组的第一线和第一空间的宽度的至少一部分大于第一线的宽度或第一空间的第一空间的宽度 均匀重复模式组。
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公开(公告)号：US07682757B2
公开(公告)日：2010-03-23
申请号：US11401837
申请日：2006-04-12
IPC分类号： G03F1/00
摘要： A pattern layout for forming an integrated circuit includes a first device pattern, a second device pattern, and an auxiliary pattern. The first device pattern includes a line and a space alternately arrayed on a fixed pitch having regular intervals in a first direction. The second device pattern is disposed on the fixed pitch and separated from the first device pattern in the first direction. The second device pattern has a pattern width an odd-number times larger than the regular intervals of the fixed pitch, wherein the odd-number is set to be three or more. The auxiliary pattern is disposed on the fixed pitch and within the second device pattern and configured not to be resolved by light exposure.
摘要翻译： 用于形成集成电路的图案布局包括第一器件图案，第二器件图案和辅助图案。 第一装置图案包括在第一方向上具有规则间隔的固定间距交替排列的线和空间。 第二装置图案设置在固定节距上并且在第一方向上与第一装置图案分离。 第二装置图案的图案宽度比固定间距的规则间隔大奇数倍，其中奇数被设定为三个以上。 辅助图案设置在固定间距上并且在第二装置图案内并且被配置为不被曝光解决。
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公开(公告)号：US20060228636A1
公开(公告)日：2006-10-12
申请号：US11401837
申请日：2006-04-12
摘要： A pattern layout for forming an integrated circuit includes a first device pattern, a second device pattern, and an auxiliary pattern. The first device pattern includes a line and a space alternately arrayed on a fixed pitch having regular intervals in a first direction. The second device pattern is disposed on the fixed pitch and separated from the first device pattern in the first direction. The second device pattern has a pattern width an odd-number times larger than the regular intervals of the fixed pitch, wherein the odd-number is set to be three or more. The auxiliary pattern is disposed on the fixed pitch and within the second device pattern and configured not to be resolved by light exposure.
摘要翻译： 用于形成集成电路的图案布局包括第一器件图案，第二器件图案和辅助图案。 第一装置图案包括在第一方向上具有规则间隔的固定间距交替排列的线和空间。 第二装置图案设置在固定节距上并且在第一方向上与第一装置图案分离。 第二装置图案的图案宽度比固定间距的规则间隔大奇数倍，其中奇数被设定为三个以上。 辅助图案设置在固定间距上并且在第二装置图案内并且被配置为不被曝光解决。
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公开(公告)号：US20100202181A1
公开(公告)日：2010-08-12
申请号：US12561531
申请日：2009-09-17
申请人： Takaki HASHIMOTO , Hidefumi Mukai , Yasunobu Kai , Toshiya Kotani
发明人： Takaki HASHIMOTO , Hidefumi Mukai , Yasunobu Kai , Toshiya Kotani
IPC分类号： G11C5/06
摘要： A semiconductor memory device includes a semiconductor substrate on which memory cells are formed. Interconnects are arranged along a first direction above the semiconductor substrate, and have regular intervals along a second direction perpendicular to the first direction. Interconnect contacts connect the interconnects and the semiconductor substrate, are arranged on three or more rows. The center of each of two of the interconnect contacts which are connected to the interconnects adjacent in the second direction deviate from each other along the first direction.
摘要翻译： 半导体存储器件包括形成有存储单元的半导体衬底。 互连件沿着半导体衬底上方的第一方向布置，并且沿着垂直于第一方向的第二方向具有规则的间隔。 互连触点连接互连和半导体衬底，布置在三行或更多行上。 连接到在第二方向相邻的互连件的两个互连触点中的每一个的中心沿着第一方向彼此偏离。
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5.发明授权Parameter adjustment method, semiconductor device manufacturing method, and recording medium 有权参数调整方法，半导体器件制造方法和记录介质公开(公告)号：US07934175B2
公开(公告)日：2011-04-26
申请号：US12062859
申请日：2008-04-04
申请人： Toshiya Kotani , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
发明人： Toshiya Kotani , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
IPC分类号： G06F17/50
CPC分类号： G03F7/70625 , G03F7/70525 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate; defining an adjustable parameter of another to-be-adjusted manufacturing; obtaining a second shape of the pattern formed on the substrate; calculating a difference amount between a reference finished shape and a to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; and outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter.
摘要翻译： 用于使用该制造装置在基板上形成半导体器件的图案的多个制造装置的参数调整方法包括：调整可用于作为参考制造装置的制造装置的参数; 获得要在基板上形成的半导体器件的图案的第一形状; 定义另一个待调整制造的可调参数; 获得形成在所述基板上的所述图案的第二形状; 计算参考完成形状和待调整完成形状之间的差值; 通过改变待调整参数重复计算差值，直到差值变得等于或小于预定参考值; 并作为待调整制造装置的参数输出待调整参数。
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公开(公告)号：US20090142706A1
公开(公告)日：2009-06-04
申请号：US12257968
申请日：2008-10-24
申请人： Kazuyuki Masukawa , Koji Hashimoto , Kenji Kawano , Yasunobu Kai
发明人： Kazuyuki Masukawa , Koji Hashimoto , Kenji Kawano , Yasunobu Kai
IPC分类号： G03F7/20
CPC分类号： G03F7/70466 , G03F1/36 , G03F1/70 , G03F7/70425 , G03F7/70441
摘要： A method of manufacturing a semiconductor includes performing exposure using a first photomask having a pattern line in which hole patterns and assist patterns not transferred onto the semiconductor substrate are arrayed at an equal pitch on the mask, the pitch being converted a first pitch Phole on the substrate when the mask patterns are transferred on the substrate, and performing exposure using a second photomask having a pattern line in which wiring patterns are arrayed at an equal pitch on the mask, the pitch being converted a second pitch Pline on the substrate when the mask patterns are transferred on the substrate, wherein m×Pline=n×Phole and m,n(m>n) are integers.
摘要翻译： 制造半导体的方法包括使用具有图案线的第一光掩模进行曝光，其中未转印到半导体衬底上的孔图案和辅助图案以等间距排列在掩模上，该间距将第一节距P孔转换为 衬底，当掩模图案被转印到衬底上时，并且使用具有其中布线图案以等间距排列在掩模上的图案线的第二光掩模进行曝光，当掩模在衬底上时，间距被转换为衬底上的第二间距Pline 图案转移到基板上，其中mxPline = nxPhole，m，n（m> n）是整数。
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7.发明申请PARAMETER ADJUSTMENT METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND RECORDING MEDIUM 有权参数调整方法，半导体器件制造方法和记录介质公开(公告)号：US20080250381A1
公开(公告)日：2008-10-09
申请号：US12062859
申请日：2008-04-04
申请人： Toshiya KOTANI , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
发明人： Toshiya KOTANI , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
IPC分类号： G06F17/50
CPC分类号： G03F7/70625 , G03F7/70525 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device so as to fall within a range of a predetermined permissible variation and defining the adjusted parameter as a reference parameter of the reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate using the reference manufacturing device from a mask to form the pattern on the substrate when the reference parameter is set to the reference manufacturing device and defining the obtained first shape as a reference finished shape; defining an adjustable parameter of another to-be-adjusted manufacturing device as a to-be-adjusted parameter of the to-be-adjusted manufacturing device; obtaining a second shape of the pattern formed on the substrate using the to-be-adjusted manufacturing device from the mask when the defined to-be-adjusted parameter is set to the to-be-adjusted manufacturing device and defining the obtained second shape as a to-be-adjusted finished shape; calculating a difference amount between the reference finished shape and the to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter having the difference amount equal to or less than the predetermined reference value or the to-be-adjusted parameter having the difference amount which becomes equal to or less than the predetermined reference value through the repeated calculation.
摘要翻译： 用于使用该制造装置在基板上形成半导体器件的图案的多个制造装置的参数调整方法包括：调整作为参考制造装置的制造装置可调节的参数，使其落在 预定的允许变化并将调整参数定义为参考制造装置的参考参数; 使用参考制造装置从掩模获得要在基板上形成的半导体器件的图案的第一形状，以在将参考参数设置为参考制造装置并将所获得的第一形状定义为 参考完成形状; 将另一个待调节制造装置的可调参数定义为待调整制造装置的待调整参数; 当将所述规定的待调整参数设定为所述待调节制造装置并且将所获得的第二形状定义为所述第二形状时，从所述掩模获得使用所述待调节制造装置在所述基板上形成的所述图案的第二形状 一个待调整的成品形状; 计算参考完成形状和待调整完成形状之间的差值; 通过改变待调整参数重复计算差值，直到差值变得等于或小于预定参考值; 作为待调整制造装置的参数输出具有等于或小于预定参考值的差值的待调整参数或具有等于或等于或等于或等于 通过重复计算小于预定的参考值。
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8.发明授权
公开(公告)号：US5128465A
公开(公告)日：1992-07-07
申请号：US468319
申请日：1990-01-22
申请人： Takashi Kamiya , Toshihiko Naito , Yuuki Komatu , Yasunobu Kai , Takaharu Nakamura , Manabu Sasho , Shigeto Negi , Isao Sugiyama , Kanemasa Katsu , Hiroshi Yamauchi
发明人： Takashi Kamiya , Toshihiko Naito , Yuuki Komatu , Yasunobu Kai , Takaharu Nakamura , Manabu Sasho , Shigeto Negi , Isao Sugiyama , Kanemasa Katsu , Hiroshi Yamauchi
IPC分类号： C07D498/04 , C07C237/06 , C07D498/08 , C07D501/00 , C07D501/18 , C07D501/24 , C07D501/46 , C07D501/56 , C07D519/00
CPC分类号： C07D498/08 , C07C237/06 , C07D501/00 , Y02P20/55
摘要： A cephem derivative represented by the following formula: ##STR1## wherein R.sub.1 means a fluorine-substituted lower alkyl and A.sub.1 denotes a cyclic or acyclic ammonio group, or a non-toxic salt thereof, is prepared by reacting a compound represented by the following formula: ##STR2## wherein A.sub.1 has the same meaning as defined above, with another compound represented by the following formula: ##STR3## wherein R.sub.1 has the same meaning as defined above, and if necessary, removing the protecting groups.
摘要翻译： 由下式表示的头孢烯衍生物：其中R1表示氟取代的低级烷基，A1表示环状或无环氨基，或其无毒盐，通过使下式表示的化合物 其中A 1具有与上述定义相同的含义，另外由下式表示的化合物：其中R 1具有与上述相同的含义，如有必要，除去保护基。
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公开(公告)号：US08865589B2
公开(公告)日：2014-10-21
申请号：US13614217
申请日：2012-09-13
申请人： Takaki Hashimoto , Yasunobu Kai , Toshiya Kotani
发明人： Takaki Hashimoto , Yasunobu Kai , Toshiya Kotani
IPC分类号： H01L21/027 , H01L21/768 , H01L21/311 , H01L23/528 , H01L21/033 , H01L27/115
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/31144 , H01L21/768 , H01L21/76804 , H01L21/76816 , H01L21/76895 , H01L27/11519 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality at first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires.
摘要翻译： 根据一个实施例，半导体器件包括以预定间距平行布置的多条导线，多个第一触点分别连接到导线之间的奇数编号，并且与正交方向平行布置，与 与导线的布线方向相连接的多个第二触点，以及多个第二触点，每个第二触点各自连接到电线中的偶数线，并且相对于线的布线方向在正交方向上平行布置， 在与导线的布线方向正交的方向上的第一触点相对于第二触点偏离线的间距的方式偏离布线方向的第一触点。
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公开(公告)号：US08293456B2
公开(公告)日：2012-10-23
申请号：US12390157
申请日：2009-02-20
IPC分类号： G03F1/00
CPC分类号： G03F1/00 , G03F1/36 , G03F7/70433
摘要： A semiconductor device manufacturing method includes applying illumination light to a photomask, and projecting diffracted light components from the photomask via a projection optical system to form a photoresist pattern on a substrate. The photomask includes a plurality of opening patterns which are arranged on each of a plurality of parallel lines at regular second intervals in a second direction and which have regular first intervals in a first direction perpendicular to the second direction. The plurality of opening patterns arranged on the adjacent ones of the plurality of parallel lines are displaced from each other half the second interval in the second direction. Moreover, the dimensions of the plurality of opening patterns and the complex amplitude transmittance of nontransparent region in the photomask are set so that three of the diffracted light components passing through the pupil of the projection optical system have equal amplitude.
摘要翻译： 一种半导体器件制造方法，包括将照明光施加到光掩模，以及经由投影光学系统从光掩模投射衍射光成分，以在基板上形成光刻胶图案。 光掩模包括多个开口图案，其以在第二方向上的规则的第二间隔布置在多条平行线中的每一条上，并且在垂直于第二方向的第一方向上具有规则的第一间隔。 布置在多条平行线上相邻的多个平行线上的多个开口图案在第二方向上相互偏移第二间隔的一半。 此外，设置多个开口图案的尺寸和光掩模中的非透明区域的复振幅透射率，使得穿过投影光学系统的光瞳的三个衍射光分量具有相等的幅度。
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