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    SEMICONDUCTOR DEVICE AND WIRELESS COMMUNICATION SYSTEM USING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND WIRELESS COMMUNICATION SYSTEM USING THE SAME 有权
    半导体器件和无线通信系统

    公开(公告)号：US20110315780A1

    公开(公告)日：2011-12-29

    申请号：US13226770

    申请日：2011-09-07

    申请人： Tomoaki ATSUMI ,  Yutaka SHIONOIRI ,  Hidetomo KOBAYASHI

    发明人： Tomoaki ATSUMI ,  Yutaka SHIONOIRI ,  Hidetomo KOBAYASHI

    IPC分类号： G06K19/073

    CPC分类号： G06K19/07749 ,  G06K19/0708

    摘要： Initialization of a semiconductor device can be efficiently performed, which transmits and receives data through wireless communication. The semiconductor device includes an antenna, a power source circuit, a circuit which uses a DC voltage generated by the power source circuit as a power source voltage, and a resistor. The antenna includes a pair of terminals and receives a wireless signal (a modulated carrier wave). The power source circuit includes a first terminal and a second terminal and generates a DC voltage between the first terminal and the second terminal by using a received wireless signal (the modulated carrier wave). The resistor is connected between the first terminal and the second terminal. In this manner, the semiconductor device and the wireless communication system can transmit and receive data accurately.

    摘要翻译： 可以有效地执行半导体器件的初始化，其通过无线通信发送和接收数据。 半导体器件包括天线，电源电路，使用由电源电路产生的直流电压作为电源电压的电路和电阻器。 天线包括一对终端，并接收无线信号（调制载波）。 电源电路包括第一端子和第二端子，并且通过使用接收的无线信号（调制载波）在第一端子和第二端子之间产生直流电压。 电阻器连接在第一端子和第二端子之间。 以这种方式，半导体器件和无线通信系统可以准确地发送和接收数据。

    SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF 有权
    半导体器件及其驱动方法

    公开(公告)号：US20120275214A1

    公开(公告)日：2012-11-01

    申请号：US13455188

    申请日：2012-04-25

    申请人： Tomoaki ATSUMI ,  Yoshiya TAKEWAKI

    发明人： Tomoaki ATSUMI ,  Yoshiya TAKEWAKI

    IPC分类号： G11C11/24

    CPC分类号： G11C5/10 ,  G11C11/401 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4099 ,  H01L27/10873 ,  H01L27/10897 ,  H01L27/1218 ,  H01L27/1225

    摘要： In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.

    摘要翻译： 在包括具有排列成矩阵的存储单元的存储单元阵列的存储器模块中，每个存储单元包括使用氧化物半导体的第一晶体管和第一电容器; 包括p沟道第三晶体管，第二电容器和使用氧化物半导体的第二晶体管的参考单元; 以及包括电阻器和比较器的刷新定时检测电路，其中当通过第一晶体管向第一电容器提供电位时，通过第二晶体管将电位提供给第二电容器，其中第三晶体管的漏极电流值 根据存储在第二电容器中的电位而改变，并且当第三晶体管的漏极电流值高于给定值时，执行存储单元阵列和参考单元的刷新操作。

    CYCLIC REDUNDANCY CHECK CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE CYCLIC REDUNDANCY CHECK CIRCUIT
    5.
    发明申请
    CYCLIC REDUNDANCY CHECK CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE CYCLIC REDUNDANCY CHECK CIRCUIT 有权
    循环冗余检查电路和具有循环冗余检查电路的半导体器件

    公开(公告)号：US20070089028A1

    公开(公告)日：2007-04-19

    申请号：US11533169

    申请日：2006-09-19

    申请人： Masafumi ITO ,  Tomoaki ATSUMI

    发明人： Masafumi ITO ,  Tomoaki ATSUMI

    IPC分类号： H03M13/00

    CPC分类号： H03M13/09 ,  H04B1/10

    摘要： An object of the present invention is to provide a CRC circuit with more simple structure and low power consumption. The CRC circuit includes a first shift register to a p-th shift register, a first EXOR to a (p−1)th EXOR, and a switching circuit. A data signal, a select signal, and an output of a last stage of the p-th shift register are inputted to the switching circuit, and the switching circuit switches a first signal or a second signal in response to the select signal to be outputted.

    摘要翻译： 本发明的目的是提供一种具有更简单的结构和低功耗的CRC电路。 CRC电路包括到第p移位寄存器的第一移位寄存器，第一EXOR到第（p-1）个EXOR和开关电路。 数据信号，选择信号和第p移位寄存器的最后级的输出被输入到开关电路，并且开关电路响应于要输出的选择信号而切换第一信号或第二信号 。

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件

    公开(公告)号：US20100080074A1

    公开(公告)日：2010-04-01

    申请号：US12567975

    申请日：2009-09-28

    申请人： Takuro OHMARU ,  Tomoaki ATSUMI ,  Toshihiko SAITO

    发明人： Takuro OHMARU ,  Tomoaki ATSUMI ,  Toshihiko SAITO

    IPC分类号： G11C29/00

    CPC分类号： G11C29/44 ,  G11C16/3459 ,  G11C16/349 ,  G11C29/4401 ,  G11C29/808 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/4402

    摘要： Easy and fast memory access with correcting defects is to be realized. In a spare memory in a semiconductor memory device, a redundant memory cell array that stores the number of correcting defects is provided. When a signal from the outside is received, the signal is switched to the redundant memory cell array, and the number of correcting defects is judged. Then, based on the result of the judgment, it is determined the judgment of a defective memory cell is continued or the judgment is finished to write data to a main memory cell. By providing the redundant memory cell array that stores the number of correcting defects, a state of correcting defects can be observed fast in such a manner.

    摘要翻译： 要实现具有纠正缺陷的简单快速的存储器访问。 在半导体存储器件的备用存储器中，提供存储修正缺陷数量的冗余存储单元阵列。 当接收到来自外部的信号时，信号被切换到冗余存储单元阵列，并且判断校正缺陷的数量。 然后，基于判断结果，确定不良存储单元的判断继续，或判断结束，将数据写入主存储单元。 通过提供存储校正缺陷数量的冗余存储单元阵列，可以以这种方式快速观察校正缺陷的状态。