公开(公告)号：US07583219B2

公开(公告)日：2009-09-01

申请号：US12027495

申请日：2008-02-07

申请人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim ,  Seung Chul Lee

发明人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim ,  Seung Chul Lee

IPC分类号： H03M1/38

CPC分类号： H03M1/1245 ,  H03M1/002 ,  H03M1/44

摘要： Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC.

摘要翻译： 提供了没有前端采样保持放大器（SHA）的管线模数转换器（ADC）及其控制方法。 该方法包括以下步骤：在ADC和包括在第一级中的残余信号发生器同时对模拟输入信号进行采样，并分别产生第一采样值和第二采样值; 在剩余信号发生器处保持​​第二采样值，并且同时在ADC处放大并转换第一采样值为相应的数字代码; 以及在剩余信号发生器处产生使用数字码的残留信号。 流水线ADC和控制相同的方法最小化了通过去除前端SHA引起的采样失配，从而确保了没有前端SHA的稳定性能。 由于不使用前端SHA，因此可以减少芯片尺寸和功耗，并提高ADC的性能。

公开(公告)号：US07683706B2

公开(公告)日：2010-03-23

申请号：US12195202

申请日：2008-08-20

申请人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03F1/02

CPC分类号： H03F3/005

摘要： Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized.

摘要翻译： 提供一种增益放大器，其具有能够最小化建立时间的开关电容器结构，其中输入电容器在第一时钟对输入信号进行采样期间连接到输入端子，因此放大器的输出端子预先复位到 输入电容器的估计输出电压值而不是0。 因此，放大器的输出端子的轻微移动足以在放大模式下稳定到期望值，从而可以减少回转时间，结果可以使整体建立时间和功耗最小化。

公开(公告)号：US20090091383A1

公开(公告)日：2009-04-09

申请号：US12195202

申请日：2008-08-20

申请人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03F1/00

CPC分类号： H03F3/005

摘要： Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized.

摘要翻译： 提供一种增益放大器，其具有能够最小化建立时间的开关电容器结构，其中输入电容器在第一时钟对输入信号进行采样期间连接到输入端子，因此放大器的输出端子预先复位到 输入电容器的估计输出电压值而不是0。 因此，放大器的输出端子的轻微移动足以在放大模式下稳定到期望值，从而可以减少回转时间，结果可以使整体建立时间和功耗最小化。

公开(公告)号：US20080068237A1

公开(公告)日：2008-03-20

申请号：US11695143

申请日：2007-04-02

申请人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03M1/12

CPC分类号： H03M1/1225 ,  H03M1/168

摘要： Provided is a multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure. The multi-bit pipeline ADC includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage and removing a sampling error of the input voltage; N-bit flash ADCs of first to K-th stages receiving analog signals, converting them into digital signals and outputting the digital signals; N-bit multiplying digital-to-analog converters (MDACs) of first to K-th stages converting differences between the digital signals output from the N-bit flash ADCs and output signals of preceding stages back into analog signals and outputting the analog signals; and a three-stage amplifier connected with an output of the N-bit MDAC of the first stage at a first clock and an output of the SHA at a second clock, wherein N is an integer greater than or equal to 1 and K is an integer greater than or equal to 2.In the multi-bit pipeline ADC, an amplifier can be shared between an SHA consuming much power and an MDAC of a first stage, so that power consumption and chip size can be reduced.

摘要翻译： 提供了具有共享放大器结构的多位流水线模数转换器（ADC）。 多位流水线ADC包括：采样和保持放大器（SHA），用于采样和保持输入模拟电压并消除输入电压的采样误差; 第一至第K级的N位闪存ADC接收模拟信号，将其转换为数字信号并输出​​数字信号; 第一到第K级的N位乘法数模转换器（MDAC）将从N位闪存ADC输出的数字信号与前级的输出信号之间的差值转换成模拟信号并输出​​模拟信号; 以及在第一时钟与第一级的N位MDAC的输出和第二时钟的SHA的输出连接的三级放大器，其中N是大于或等于1的整数，并且K是 整数大于或等于2.在多位流水线ADC中，可以在消耗大量功率的SHA和第一级的MDAC之间共享放大器，从而可以降低功耗和芯片尺寸。

公开(公告)号：US07397409B2

公开(公告)日：2008-07-08

申请号：US11695143

申请日：2007-04-02

申请人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03M1/12

CPC分类号： H03M1/1225 ,  H03M1/168

摘要： A multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage and removing a sampling error of the input voltage; N-bit flash ADCs of first to K-th stages receiving analog signals, converting them into digital signals and outputting the digital signals; N-bit multiplying digital-to-analog converters (MDACs) of first to K-th stages converting differences between the digital signals output from the N-bit flash ADCs and output signals of preceding stages back into analog signals and outputting the analog signals; and a three-stage amplifier connected to an output of the N-bit MDAC of the first stage at a first clock and an output of the SHA at a second clock, wherein intergers N>= and K>=2. An amplifier can be shared between an SHA and an MDAC of a first stage, thereby reducing power consumption and chip size.In the multi-bit pipeline ADC, an amplifier can be shared between an SHA consuming much power and an MDAC of a first stage, so that power consumption and chip size can be reduced.

摘要翻译： 具有共享放大器结构的多位流水线模数转换器（ADC）包括：采样和保持放大器（SHA），用于采样和保持输入模拟电压并去除输入电压的采样误差; 第一至第K级的N位闪存ADC接收模拟信号，将其转换为数字信号并输出​​数字信号; 第一到第K级的N位乘法数模转换器（MDAC）将从N位闪存ADC输出的数字信号与前级的输出信号之间的差值转换成模拟信号并输出​​模拟信号; 以及三级放大器，在第一时钟连接到第一级的N位MDAC的输出，在第二时钟连接到SHA的输出，其中，间隔N> =且K> = 2。 放大器可以在第一级的SHA和MDAC之间共享，从而降低功耗和芯片尺寸。 在多位流水线ADC中，放大器可以在消耗大量功率的SHA和第一级的MDAC之间共享，从而可以降低功耗和芯片尺寸。

公开(公告)号：US07482966B2

公开(公告)日：2009-01-27

申请号：US11946583

申请日：2007-11-28

申请人： Seung Chul Lee ,  Young Deuk Jeon ,  Kwi Dong Kim ,  Jong Kee Kwon

发明人： Seung Chul Lee ,  Young Deuk Jeon ,  Kwi Dong Kim ,  Jong Kee Kwon

IPC分类号： H03M1/38

CPC分类号： H03M1/0678 ,  H03M1/162

摘要： Provided is an algorithm analog-to-digital converter (ADC). The algorithm ADC obtains two digital outputs through different capacitor connections for one analog input signal and adds the digital output signals to obtain a final output value, so that a mismatch factor of the capacitor is removed to minimize a linearity limitation resulting from the capacitor mismatch. In addition, the algorithm ADC minimizes power consumption by making the operating frequency slow at a cycle requiring a high resolution and making the operating frequency fast at a cycle requiring a low resolution, i.e., outputting different operating clock frequencies according to a required resolution.

摘要翻译： 提供了一种算法模数转换器（ADC）。 算法ADC通过不同的电容器连接获得两个数字输出，用于一个模拟输入信号，并将数字输出信号相加以获得最终输出值，从而消除电容器的失配因子，以最小化由电容器失配引起的线性限制。 此外，算法ADC通过使工作频率在需要高分辨率的周期中变慢，并使工作频率在需要低分辨率的周期（即，根据所需分辨率输出不同的工作时钟频率）的情况下将功率消耗最小化。

公开(公告)号：US20090091387A1

公开(公告)日：2009-04-09

申请号：US12195212

申请日：2008-08-20

申请人： Young Kyun CHO ,  Young Deuk Jeon ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Young Kyun CHO ,  Young Deuk Jeon ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03G3/30

CPC分类号： H03G1/0094 ,  H03F3/005 ,  H03F3/45475

摘要： Provided is a switched-capacitor variable gain amplifier having high voltage gain linearity. According to the above amplifier, a sampling capacitor is shared and used at a sampling phase and an amplification phase, and thus a voltage gain error caused by capacitor mismatch can be reduced. Also, using a unit capacitor array enables circuit design and layout to be simplified. Further, in the amplifier, a voltage gain can be easily controlled to be more or less than 1, as necessary, and power consumption and kT/C noise can be reduced by a feedback factor that is relatively large, so that gain amplification performance can be improved.

摘要翻译： 提供了具有高电压增益线性度的开关电容器可变增益放大器。 根据上述放大器，采样电容器在采样相位和放大阶段被共享并使用，因此可以减小由电容器失配引起的电压增益误差。 此外，使用单位电容阵列可以简化电路设计和布局。 此外，在放大器中，根据需要，可以容易地将电压增益控制为大于或等于1，并且可以通过相对较大的反馈因子来降低功耗和kT / C噪声，从而增益放大性能可以 要改进

公开(公告)号：US07696819B2

公开(公告)日：2010-04-13

申请号：US12195212

申请日：2008-08-20

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03F1/36

CPC分类号： H03G1/0094 ,  H03F3/005 ,  H03F3/45475

摘要： Provided is a switched-capacitor variable gain amplifier having high voltage gain linearity. According to the above amplifier, a sampling capacitor is shared and used at a sampling phase and an amplification phase, and thus a voltage gain error caused by capacitor mismatch can be reduced. Also, using a unit capacitor array enables circuit design and layout to be simplified. Further, in the amplifier, a voltage gain can be easily controlled to be more or less than 1, as necessary, and power consumption and kT/C noise can be reduced by a feedback factor that is relatively large, so that gain amplification performance can be improved.

摘要翻译： 提供了具有高电压增益线性度的开关电容器可变增益放大器。 根据上述放大器，采样电容器在采样相位和放大阶段被共享并使用，因此可以减小由电容器失配引起的电压增益误差。 此外，使用单位电容阵列可以简化电路设计和布局。 此外，在放大器中，根据需要，可以容易地将电压增益控制为大于或等于1，并且可以通过相对较大的反馈因子来降低功耗和kT / C噪声，从而增益放大性能可以 要改进

公开(公告)号：US08164497B2

公开(公告)日：2012-04-24

申请号：US12777910

申请日：2010-05-11

申请人： Jae Won Nam ,  Young Deuk Jeon ,  Young Kyun Cho ,  Jong Kee Kwon

发明人： Jae Won Nam ,  Young Deuk Jeon ,  Young Kyun Cho ,  Jong Kee Kwon

IPC分类号： H03M1/00

CPC分类号： H03M1/0836 ,  H03M1/168

摘要： Provided is a pipeline analog-to-digital converter (ADC) without a front-end sample-and-hold amplifier (SHA). To minimize a sampling error occurring between a flash ADC and a multiplying digital-to-analog converter (MDAC) of a first sub-ranging ADC due to removal of a front-end SHA, a delay time of a preamplifier included in the flash ADC is calculated, and the flash ADC samples an analog input signal later by the delay time than the MDAC. Accordingly, the pipeline ADC can minimize a sampling error without using a front-end SHA, and its chip area and power consumption can be reduced.

摘要翻译： 提供了一种没有前端采样和保持放大器（SHA）的流水线模数转换器（ADC）。 为了最小化由于去除前端SHA而导致的闪存ADC和第一子范围ADC的乘法数模转换器（MDAC）之间的采样误差，包括在闪存ADC中的前置放大器的延迟时间 并且闪速ADC比模拟输入信号稍后采样延迟时间比MDAC。 因此，流水线ADC可以在不使用前端SHA的情况下最小化采样误差，并且可以减少其芯片面积和功耗。

公开(公告)号：US07999719B2

公开(公告)日：2011-08-16

申请号：US12433764

申请日：2009-04-30

申请人： Young Deuk Jeon ,  Young Kyun Cho ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Deuk Jeon ,  Young Kyun Cho ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03M1/38

CPC分类号： H03M1/164 ,  H03M1/468

摘要： A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same are provided. The multi-stage SAR ADC connects small-size and low-power SAR ADCs in multiple stages, thereby reducing a whole chip size and power consumption. The analog-to-digital converting method simultaneously performs analog-to-digital conversions in the SAR ADCs connected in the multiple stages, thereby reducing an analog-to-digital conversion time and maintaining an operating rate of several tens of MHz to several hundreds of MHz similar to that of a pipeline ADC.

摘要翻译： 提供了多级连续近似寄存器模数转换器（SAR ADC）和使用其的模数转换方法。 多级SAR ADC多级连接小尺寸和低功耗SAR ADC，从而降低整个芯片尺寸和功耗。 模数转换方法同时在多级连接的SAR ADC中执行模数转换，从而减少模数转换时间，并将几十MHz至几百 MHz与流水线ADC类似。