公开(公告)号：US08164497B2

公开(公告)日：2012-04-24

申请号：US12777910

申请日：2010-05-11

申请人： Jae Won Nam ,  Young Deuk Jeon ,  Young Kyun Cho ,  Jong Kee Kwon

发明人： Jae Won Nam ,  Young Deuk Jeon ,  Young Kyun Cho ,  Jong Kee Kwon

IPC分类号： H03M1/00

CPC分类号： H03M1/0836 ,  H03M1/168

摘要： Provided is a pipeline analog-to-digital converter (ADC) without a front-end sample-and-hold amplifier (SHA). To minimize a sampling error occurring between a flash ADC and a multiplying digital-to-analog converter (MDAC) of a first sub-ranging ADC due to removal of a front-end SHA, a delay time of a preamplifier included in the flash ADC is calculated, and the flash ADC samples an analog input signal later by the delay time than the MDAC. Accordingly, the pipeline ADC can minimize a sampling error without using a front-end SHA, and its chip area and power consumption can be reduced.

摘要翻译： 提供了一种没有前端采样和保持放大器（SHA）的流水线模数转换器（ADC）。 为了最小化由于去除前端SHA而导致的闪存ADC和第一子范围ADC的乘法数模转换器（MDAC）之间的采样误差，包括在闪存ADC中的前置放大器的延迟时间 并且闪速ADC比模拟输入信号稍后采样延迟时间比MDAC。 因此，流水线ADC可以在不使用前端SHA的情况下最小化采样误差，并且可以减少其芯片面积和功耗。

公开(公告)号：US08547081B2

公开(公告)日：2013-10-01

申请号：US12833841

申请日：2010-07-09

申请人： Young Deuk Jeon ,  Young Kyun Cho ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Deuk Jeon ,  Young Kyun Cho ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： G05F1/00 ,  G05F3/16 ,  G05F3/20

CPC分类号： H03F3/347

摘要： A reference voltage supply circuit is provided. The reference voltage supply circuit includes a first amplifier for amplifying a first input voltage and a fed back first reference voltage, a second amplifier for amplifying a second input voltage and a fed back second reference voltage, a reference voltage generator for generating the first reference voltage and the second reference voltage according to output signals of the first and second amplifiers and feeding the first and second reference voltages back to the first and second amplifiers, and a glitch remover turned on/off according to an input pulse signal to conduct or cut off current flowing between a power supply terminal and the ground.

摘要翻译： 提供参考电压供应电路。 参考电压供应电路包括用于放大第一输入电压和反馈第一参考电压的第一放大器，用于放大第二输入电压的第二放大器和反馈的第二参考电压;参考电压发生器，用于产生第一参考电压 以及根据第一和第二放大器的输出信号的第二参考电压，并将第一和第二参考电压馈送回第一和第二放大器，并且毛刺去除器根据输入脉冲信号导通/截止以导通或切断 在电源端子和地之间流动的电流。

公开(公告)号：US08264268B2

公开(公告)日：2012-09-11

申请号：US12843535

申请日：2010-07-26

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03L5/00

CPC分类号： H03M1/1023 ,  H03M1/66

摘要： Provided is an offset-voltage calibration circuit. The circuit includes a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages, an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator, and a current digital-to-analog converter (DAC) configured to control the amount of current supplied from a node to which the comparison voltage is applied, in response to the output signal of the UDC and control the magnitude of the comparison voltage.

摘要翻译： 提供了一种偏移电压校准电路。 所述电路包括比较器，被配置为接收至少两个比较电压并输出所述比较电压之间的比较结果;响应于所述比较电压被配置为输出递增计数或递减计数输出信号的上/下计数器（UDC） 比较器的输出信号，以及被配置为响应于UDC的输出信号来控制从施加了比较电压的节点提供的电流量的电流数模转换器（DAC），并且控制幅度 的比较电压。

公开(公告)号：US08059022B2

公开(公告)日：2011-11-15

申请号：US12773768

申请日：2010-05-04

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03M1/66

CPC分类号： H03M1/0682 ,  H03M1/468 ,  H03M1/68 ,  H03M1/682 ,  H03M1/804 ,  H03M1/806

摘要： A digital-to-analog converter (DAC) is provided. The DAC includes a positive converter, a negative converter, and a comparator for receiving outputs of the positive converter and the negative converter, comparing the outputs with a reference voltage, and generating an output voltage. Each of the positive converter and the negative converter includes an upper-bit converter including a plurality of bit capacitors corresponding to respective upper bits, a lower-bit converter including a plurality of bit capacitors corresponding to respective lower bits, and a coupling capacitor for connecting the upper-bit converter with the lower-bit converter in series. Each of the positive converter and the negative converter receives a bias voltage to have a uniform offset when converting the respective bits. Accordingly, it is possible to obtain a high resolution using a small area. Also, the number of capacitors can be reduced, and the capacitance of a unit capacitor can be maximized. Consequently, it is possible to minimize heat noise and device mismatching.

摘要翻译： 提供了数模转换器（DAC）。 DAC包括正转换器，负转换器和用于接收正转换器和负转换器的输出的比较器，将输出与参考电压进行比较，并产生输出电压。 正转换器和负转换器中的每个包括具有对应于各高位的多个位电容器的高位转换器，包括对应于各低位的多个位电容器的低位转换器和用于连接的耦合电容器 低位转换器与低位转换器串联。 正转换器和负转换器中的每一个在转换各个位时接收偏置电压以具有均匀的偏移。 因此，可以使用小面积获得高分辨率。 此外，可以减少电容器的数量，并且可以使单位电容器的电容最大化。 因此，可以最小化热噪声和器件不匹配。

公开(公告)号：US20110102220A1

公开(公告)日：2011-05-05

申请号：US12777910

申请日：2010-05-11

申请人： Jae Won NAM ,  Young Deuk Jeon ,  Young Kyun Cho ,  Jong Kee Kwon

发明人： Jae Won NAM ,  Young Deuk Jeon ,  Young Kyun Cho ,  Jong Kee Kwon

IPC分类号： H03M1/00 ,  H03M1/38

CPC分类号： H03M1/0836 ,  H03M1/168

摘要： Provided is a pipeline analog-to-digital converter (ADC) without a front-end sample-and-hold amplifier (SHA). To minimize a sampling error occurring between a flash ADC and a multiplying digital-to-analog converter (MDAC) of a first sub-ranging ADC due to removal of a front-end SHA, a delay time of a preamplifier included in the flash ADC is calculated, and the flash ADC samples an analog input signal later by the delay time than the MDAC. Accordingly, the pipeline ADC can minimize a sampling error without using a front-end SHA, and its chip area and power consumption can be reduced.

摘要翻译： 提供了一种没有前端采样和保持放大器（SHA）的流水线模数转换器（ADC）。 为了最小化由于去除前端SHA而导致的闪存ADC和第一子范围ADC的乘法数模转换器（MDAC）之间的采样误差，包括在闪存ADC中的前置放大器的延迟时间 并且闪速ADC比模拟输入信号稍后采样延迟时间比MDAC。 因此，流水线ADC可以在不使用前端SHA的情况下最小化采样误差，并且可以减少其芯片面积和功耗。

公开(公告)号：US20100123611A1

公开(公告)日：2010-05-20

申请号：US12472375

申请日：2009-05-27

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03M1/12

CPC分类号： H03M1/069 ,  H03M1/0607 ,  H03M1/468 ,  H03M1/804

摘要： A successive approximation register (SAR) analog-digital converter (ADC) and a method of driving the same are provided. The SAR ADC includes a first converting unit including a bit capacitor array corresponding to the number of bits and a correction capacitor array, a comparator outputting a high or low voltage corresponding to each capacitor according to an output voltage of the converting unit, and a correction unit correcting the output of the bit capacitor according to the output of the correction capacitor array among the high or low output of the comparator. Therefore, two bits having the same capacitance as a least significant bit (LSB) enable a digital output error to be corrected, so that a spurious free dynamic range (SFDR) of the signal converter is increased, and a signal to noise and distortion ratio (SNDR) of an output signal is improved.

摘要翻译： 提供逐次逼近寄存器（SAR）模数转换器（ADC）及其驱动方法。 SAR ADC包括：第一转换单元，包括与位数相对应的位电容阵列和校正电容器阵列;比较器，根据转换单元的输出电压输出对应于每个电容器的高电压或低电压;以及校正 单元根据比较器的高或低输出中的校正电容器阵列的输出校正位电容器的输出。 因此，具有与最低有效位（LSB）相同的电容的两个位使得能够校正数字输出误差，使得信号转换器的无杂散动态范围（SFDR）增加，并且信噪比和失真比 （SNDR）的输出信号得到改善。

公开(公告)号：US08164504B2

公开(公告)日：2012-04-24

申请号：US12882421

申请日：2010-09-15

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03M1/12

CPC分类号： H03M1/0678 ,  H03M1/0682 ,  H03M1/468

摘要： A successive approximation resistor analog digital converter (SAR ADC) includes a first conversion unit including a correction capacitor array and a bit capacitor array 2V-1 less than the number of a bit, a second conversion unit configured to differentially operate with the first conversion unit, a comparator configured to output a voltage of a high level or a low level of each capacitor according to output voltages of the first and second conversion units, a successive approximation register (SAR) logic unit configured to receive an output voltage of the comparator to convert the received output voltage into a digital signal, and a correction logic unit configured to receive the digital signal converted by the SAR logic unit and to correct a digital signal of the bit capacitor array using a correction digital signal of the correction capacitor array of the received digital signal.

摘要翻译： 逐次逼近电阻模拟数字转换器（SAR ADC）包括第一转换单元，其包括校正电容器阵列和小于位数的位电容器阵列2V-1，第二转换单元，被配置为与第一转换单元差分地操作 ，比较器，被配置为根据第一和第二转换单元的输出电压输出每个电容器的高电平或低电平的电压;逐次逼近寄存器（SAR）逻辑单元，被配置为将比较器的输出电压接收到 将接收到的输出电压转换成数字信号，以及校正逻辑单元，被配置为接收由SAR逻辑单元转换的数字信号，并且使用校正电容器阵列的校正数字信号来校正位电容器阵列的数字信号 接收数字信号。

公开(公告)号：US20110227774A1

公开(公告)日：2011-09-22

申请号：US12882421

申请日：2010-09-15

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03M1/12

CPC分类号： H03M1/0678 ,  H03M1/0682 ,  H03M1/468

摘要： A successive approximation resistor analog digital converter (SAR ADC) includes a first conversion unit including a correction capacitor array and a bit capacitor array 2ν-1 less than the number of a bit, a second conversion unit configured to differentially operate with the first conversion unit, a comparator configured to output a voltage of a high level or a low level of each capacitor according to output voltages of the first and second conversion units, a successive approximation register (SAR) logic unit configured to receive an output voltage of the comparator to convert the received output voltage into a digital signal, and a correction logic unit configured to receive the digital signal converted by the SAR logic unit and to correct a digital signal of the bit capacitor array using a correction digital signal of the correction capacitor array of the received digital signal.

摘要翻译： 逐次逼近电阻模拟数字转换器（SAR ADC）包括第一转换单元，其包括校正电容器阵列和小于位数的位电容器阵列2＆ngr; -1，第二转换单元，被配置为与第一转换差分地操作 单元，比较器，被配置为根据第一和第二转换单元的输出电压输出每个电容器的高电平或低电平的电压;逐次逼近寄存器（SAR）逻辑单元，被配置为接收比较器的输出电压 将所接收的输出电压转换为数字信号，以及校正逻辑单元，被配置为接收由SAR逻辑单元转换的数字信号，并使用校正电容阵列的校正数字信号校正位电容阵列的数字信号 接收数字信号。

公开(公告)号：US07978117B2

公开(公告)日：2011-07-12

申请号：US12539406

申请日：2009-08-11

申请人： Young Deuk Jeon ,  Young Kyun Cho ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Deuk Jeon ,  Young Kyun Cho ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03M1/34

CPC分类号： H03M1/164 ,  H03M1/1215 ,  H03M1/468 ,  H03M1/804

摘要： A multi-stage dual successive approximation register analog-to-digital converter (SAR ADC) and a method of performing analog-to-digital conversion using the same are provided. The multi-stage dual SAR ADC includes: a plurality of SAR ADC stages for converting an analog input voltage into a predetermined bit digital signal, each SAR ADC stage being serially connected to one another and including two SAR ADCs; and at least one residue amplifier respectively connected between every two successive SAR ADC stages, amplifying residue voltage output from a previous SAR ADC stage to output the amplified residue voltage to a next SAR ADC stage. The two SAR ADCs of the previous SAR ADC stage share the residue amplifier.

摘要翻译： 提供了多级双逐次逼近寄存器模数转换器（SAR ADC）和使用其进行模数转换的方法。 多级双SAR ADC包括：多个SAR ADC级，用于将模拟输入电压转换为预定位数字信号，每个SAR ADC级串联连接并包括两个SAR ADC; 和分别连接在每两个连续的SAR ADC级之间的至少一个残余放大器，放大从先前的SAR ADC级输出的剩余电压，以将放大的残余电压输出到下一个SAR ADC级。 前一个SAR ADC级的两个SAR ADC共享残留放大器。

公开(公告)号：US07893860B2

公开(公告)日：2011-02-22

申请号：US12472375

申请日：2009-05-27

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03M1/38

CPC分类号： H03M1/069 ,  H03M1/0607 ,  H03M1/468 ,  H03M1/804

摘要： A successive approximation register (SAR) analog-digital converter (ADC) and a method of driving the same are provided. The SAR ADC includes a first converting unit including a bit capacitor array corresponding to the number of bits and a correction capacitor array, a comparator outputting a high or low voltage corresponding to each capacitor according to an output voltage of the converting unit, and a correction unit correcting the output of the bit capacitor according to the output of the correction capacitor array among the high or low output of the comparator. Therefore, two bits having the same capacitance as a least significant bit (LSB) enable a digital output error to be corrected, so that a spurious free dynamic range (SFDR) of the signal converter is increased, and a signal to noise and distortion ratio (SNDR) of an output signal is improved.

摘要翻译： 提供逐次逼近寄存器（SAR）模数转换器（ADC）及其驱动方法。 SAR ADC包括：第一转换单元，包括与位数相对应的位电容阵列和校正电容器阵列;比较器，根据转换单元的输出电压输出对应于每个电容器的高电压或低电压;以及校正 单元根据比较器的高或低输出中的校正电容器阵列的输出校正位电容器的输出。 因此，具有与最低有效位（LSB）相同的电容的两个位使得能够校正数字输出误差，使得信号转换器的无杂散动态范围（SFDR）增加，并且信噪比和失真比 （SNDR）的输出信号得到改善。