公开(公告)号：US07683706B2

公开(公告)日：2010-03-23

申请号：US12195202

申请日：2008-08-20

申请人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03F1/02

CPC分类号： H03F3/005

摘要： Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized.

摘要翻译： 提供一种增益放大器，其具有能够最小化建立时间的开关电容器结构，其中输入电容器在第一时钟对输入信号进行采样期间连接到输入端子，因此放大器的输出端子预先复位到 输入电容器的估计输出电压值而不是0。 因此，放大器的输出端子的轻微移动足以在放大模式下稳定到期望值，从而可以减少回转时间，结果可以使整体建立时间和功耗最小化。

公开(公告)号：US07696819B2

公开(公告)日：2010-04-13

申请号：US12195212

申请日：2008-08-20

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03F1/36

CPC分类号： H03G1/0094 ,  H03F3/005 ,  H03F3/45475

摘要： Provided is a switched-capacitor variable gain amplifier having high voltage gain linearity. According to the above amplifier, a sampling capacitor is shared and used at a sampling phase and an amplification phase, and thus a voltage gain error caused by capacitor mismatch can be reduced. Also, using a unit capacitor array enables circuit design and layout to be simplified. Further, in the amplifier, a voltage gain can be easily controlled to be more or less than 1, as necessary, and power consumption and kT/C noise can be reduced by a feedback factor that is relatively large, so that gain amplification performance can be improved.

摘要翻译： 提供了具有高电压增益线性度的开关电容器可变增益放大器。 根据上述放大器，采样电容器在采样相位和放大阶段被共享并使用，因此可以减小由电容器失配引起的电压增益误差。 此外，使用单位电容阵列可以简化电路设计和布局。 此外，在放大器中，根据需要，可以容易地将电压增益控制为大于或等于1，并且可以通过相对较大的反馈因子来降低功耗和kT / C噪声，从而增益放大性能可以 要改进

公开(公告)号：US07583219B2

公开(公告)日：2009-09-01

申请号：US12027495

申请日：2008-02-07

申请人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim ,  Seung Chul Lee

发明人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim ,  Seung Chul Lee

IPC分类号： H03M1/38

CPC分类号： H03M1/1245 ,  H03M1/002 ,  H03M1/44

摘要： Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC.

摘要翻译： 提供了没有前端采样保持放大器（SHA）的管线模数转换器（ADC）及其控制方法。 该方法包括以下步骤：在ADC和包括在第一级中的残余信号发生器同时对模拟输入信号进行采样，并分别产生第一采样值和第二采样值; 在剩余信号发生器处保持​​第二采样值，并且同时在ADC处放大并转换第一采样值为相应的数字代码; 以及在剩余信号发生器处产生使用数字码的残留信号。 流水线ADC和控制相同的方法最小化了通过去除前端SHA引起的采样失配，从而确保了没有前端SHA的稳定性能。 由于不使用前端SHA，因此可以减少芯片尺寸和功耗，并提高ADC的性能。

公开(公告)号：US20090091383A1

公开(公告)日：2009-04-09

申请号：US12195202

申请日：2008-08-20

申请人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03F1/00

CPC分类号： H03F3/005

摘要： Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized.

摘要翻译： 提供一种增益放大器，其具有能够最小化建立时间的开关电容器结构，其中输入电容器在第一时钟对输入信号进行采样期间连接到输入端子，因此放大器的输出端子预先复位到 输入电容器的估计输出电压值而不是0。 因此，放大器的输出端子的轻微移动足以在放大模式下稳定到期望值，从而可以减少回转时间，结果可以使整体建立时间和功耗最小化。

公开(公告)号：US08362938B2

公开(公告)日：2013-01-29

申请号：US12982531

申请日：2010-12-30

申请人： Young Kyun Cho ,  Young-deuk Jeon ,  Jaewon Nam ,  Jong-Kee Kwon

发明人： Young Kyun Cho ,  Young-deuk Jeon ,  Jaewon Nam ,  Jong-Kee Kwon

IPC分类号： H03M1/12

CPC分类号： H03M1/145 ,  H03M1/365 ,  H03M1/468

摘要： Provided is an analog digital converting device which consumes a low power and guarantees fast operation characteristic. The analog digital converting device includes a sub-ADC and a successive approximation ADC. The sub-ADC converts an external analog signal into a first digital signal by using first and second reference voltages. The successive approximation ADC comprises a plurality of bit streams, and converts the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The successive approximation ADC receives the first digital signal, and converts the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal.

摘要翻译： 提供了一种消耗低功耗并保证快速操作特性的模拟数字转换装置。 模拟数字转换装置包括子ADC和逐次逼近ADC。 子ADC通过使用第一和第二参考电压将外部模拟信号转换为第一数字信号。 逐次逼近ADC包括多个比特流，并且根据使用第一和第二参考电压的逐次逼近操作将外部模拟信号转换为第二数字信号。 逐次逼近ADC接收第一数字信号，并且在第一和第二参考电压中的一个被基于第一数字信号施加到比特流的状态下转换第二数字信号。

公开(公告)号：US08164497B2

公开(公告)日：2012-04-24

申请号：US12777910

申请日：2010-05-11

申请人： Jae Won Nam ,  Young Deuk Jeon ,  Young Kyun Cho ,  Jong Kee Kwon

发明人： Jae Won Nam ,  Young Deuk Jeon ,  Young Kyun Cho ,  Jong Kee Kwon

IPC分类号： H03M1/00

CPC分类号： H03M1/0836 ,  H03M1/168

摘要： Provided is a pipeline analog-to-digital converter (ADC) without a front-end sample-and-hold amplifier (SHA). To minimize a sampling error occurring between a flash ADC and a multiplying digital-to-analog converter (MDAC) of a first sub-ranging ADC due to removal of a front-end SHA, a delay time of a preamplifier included in the flash ADC is calculated, and the flash ADC samples an analog input signal later by the delay time than the MDAC. Accordingly, the pipeline ADC can minimize a sampling error without using a front-end SHA, and its chip area and power consumption can be reduced.

摘要翻译： 提供了一种没有前端采样和保持放大器（SHA）的流水线模数转换器（ADC）。 为了最小化由于去除前端SHA而导致的闪存ADC和第一子范围ADC的乘法数模转换器（MDAC）之间的采样误差，包括在闪存ADC中的前置放大器的延迟时间 并且闪速ADC比模拟输入信号稍后采样延迟时间比MDAC。 因此，流水线ADC可以在不使用前端SHA的情况下最小化采样误差，并且可以减少其芯片面积和功耗。

公开(公告)号：US20120062406A1

公开(公告)日：2012-03-15

申请号：US12982531

申请日：2010-12-30

申请人： Young Kyun Cho ,  Young-deuk Jeon ,  Jaewon Nam ,  Jong-Kee Kwon

发明人： Young Kyun Cho ,  Young-deuk Jeon ,  Jaewon Nam ,  Jong-Kee Kwon

IPC分类号： H03M1/36 ,  H03M1/12

CPC分类号： H03M1/145 ,  H03M1/365 ,  H03M1/468

摘要： Provided is an analog digital converting device which consumes a low power and guarantees fast operation characteristic. The analog digital converting device includes a sub-ADC and a successive approximation ADC. The sub-ADC converts an external analog signal into a first digital signal by using first and second reference voltages. The successive approximation ADC comprises a plurality of bit streams, and converts the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The successive approximation ADC receives the first digital signal, and converts the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal.

摘要翻译： 提供了一种消耗低功耗并保证快速操作特性的模拟数字转换装置。 模拟数字转换装置包括子ADC和逐次逼近ADC。 子ADC通过使用第一和第二参考电压将外部模拟信号转换为第一数字信号。 逐次逼近ADC包括多个比特流，并且根据使用第一和第二参考电压的逐次逼近操作将外部模拟信号转换为第二数字信号。 逐次逼近ADC接收第一数字信号，并且在第一和第二参考电压中的一个被基于第一数字信号施加到比特流的状态下转换第二数字信号。

公开(公告)号：US08547081B2

公开(公告)日：2013-10-01

申请号：US12833841

申请日：2010-07-09

申请人： Young Deuk Jeon ,  Young Kyun Cho ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Deuk Jeon ,  Young Kyun Cho ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： G05F1/00 ,  G05F3/16 ,  G05F3/20

CPC分类号： H03F3/347

摘要： A reference voltage supply circuit is provided. The reference voltage supply circuit includes a first amplifier for amplifying a first input voltage and a fed back first reference voltage, a second amplifier for amplifying a second input voltage and a fed back second reference voltage, a reference voltage generator for generating the first reference voltage and the second reference voltage according to output signals of the first and second amplifiers and feeding the first and second reference voltages back to the first and second amplifiers, and a glitch remover turned on/off according to an input pulse signal to conduct or cut off current flowing between a power supply terminal and the ground.

摘要翻译： 提供参考电压供应电路。 参考电压供应电路包括用于放大第一输入电压和反馈第一参考电压的第一放大器，用于放大第二输入电压的第二放大器和反馈的第二参考电压;参考电压发生器，用于产生第一参考电压 以及根据第一和第二放大器的输出信号的第二参考电压，并将第一和第二参考电压馈送回第一和第二放大器，并且毛刺去除器根据输入脉冲信号导通/截止以导通或切断 在电源端子和地之间流动的电流。

公开(公告)号：US08264268B2

公开(公告)日：2012-09-11

申请号：US12843535

申请日：2010-07-26

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03L5/00

CPC分类号： H03M1/1023 ,  H03M1/66

摘要： Provided is an offset-voltage calibration circuit. The circuit includes a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages, an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator, and a current digital-to-analog converter (DAC) configured to control the amount of current supplied from a node to which the comparison voltage is applied, in response to the output signal of the UDC and control the magnitude of the comparison voltage.

摘要翻译： 提供了一种偏移电压校准电路。 所述电路包括比较器，被配置为接收至少两个比较电压并输出所述比较电压之间的比较结果;响应于所述比较电压被配置为输出递增计数或递减计数输出信号的上/下计数器（UDC） 比较器的输出信号，以及被配置为响应于UDC的输出信号来控制从施加了比较电压的节点提供的电流量的电流数模转换器（DAC），并且控制幅度 的比较电压。

公开(公告)号：US08059022B2

公开(公告)日：2011-11-15

申请号：US12773768

申请日：2010-05-04

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03M1/66

CPC分类号： H03M1/0682 ,  H03M1/468 ,  H03M1/68 ,  H03M1/682 ,  H03M1/804 ,  H03M1/806

摘要： A digital-to-analog converter (DAC) is provided. The DAC includes a positive converter, a negative converter, and a comparator for receiving outputs of the positive converter and the negative converter, comparing the outputs with a reference voltage, and generating an output voltage. Each of the positive converter and the negative converter includes an upper-bit converter including a plurality of bit capacitors corresponding to respective upper bits, a lower-bit converter including a plurality of bit capacitors corresponding to respective lower bits, and a coupling capacitor for connecting the upper-bit converter with the lower-bit converter in series. Each of the positive converter and the negative converter receives a bias voltage to have a uniform offset when converting the respective bits. Accordingly, it is possible to obtain a high resolution using a small area. Also, the number of capacitors can be reduced, and the capacitance of a unit capacitor can be maximized. Consequently, it is possible to minimize heat noise and device mismatching.

摘要翻译： 提供了数模转换器（DAC）。 DAC包括正转换器，负转换器和用于接收正转换器和负转换器的输出的比较器，将输出与参考电压进行比较，并产生输出电压。 正转换器和负转换器中的每个包括具有对应于各高位的多个位电容器的高位转换器，包括对应于各低位的多个位电容器的低位转换器和用于连接的耦合电容器 低位转换器与低位转换器串联。 正转换器和负转换器中的每一个在转换各个位时接收偏置电压以具有均匀的偏移。 因此，可以使用小面积获得高分辨率。 此外，可以减少电容器的数量，并且可以使单位电容器的电容最大化。 因此，可以最小化热噪声和器件不匹配。