公开(公告)号：US20080068237A1

公开(公告)日：2008-03-20

申请号：US11695143

申请日：2007-04-02

申请人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03M1/12

CPC分类号： H03M1/1225 ,  H03M1/168

摘要： Provided is a multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure. The multi-bit pipeline ADC includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage and removing a sampling error of the input voltage; N-bit flash ADCs of first to K-th stages receiving analog signals, converting them into digital signals and outputting the digital signals; N-bit multiplying digital-to-analog converters (MDACs) of first to K-th stages converting differences between the digital signals output from the N-bit flash ADCs and output signals of preceding stages back into analog signals and outputting the analog signals; and a three-stage amplifier connected with an output of the N-bit MDAC of the first stage at a first clock and an output of the SHA at a second clock, wherein N is an integer greater than or equal to 1 and K is an integer greater than or equal to 2.In the multi-bit pipeline ADC, an amplifier can be shared between an SHA consuming much power and an MDAC of a first stage, so that power consumption and chip size can be reduced.

摘要翻译： 提供了具有共享放大器结构的多位流水线模数转换器（ADC）。 多位流水线ADC包括：采样和保持放大器（SHA），用于采样和保持输入模拟电压并消除输入电压的采样误差; 第一至第K级的N位闪存ADC接收模拟信号，将其转换为数字信号并输出​​数字信号; 第一到第K级的N位乘法数模转换器（MDAC）将从N位闪存ADC输出的数字信号与前级的输出信号之间的差值转换成模拟信号并输出​​模拟信号; 以及在第一时钟与第一级的N位MDAC的输出和第二时钟的SHA的输出连接的三级放大器，其中N是大于或等于1的整数，并且K是 整数大于或等于2.在多位流水线ADC中，可以在消耗大量功率的SHA和第一级的MDAC之间共享放大器，从而可以降低功耗和芯片尺寸。

公开(公告)号：US07583219B2

公开(公告)日：2009-09-01

申请号：US12027495

申请日：2008-02-07

申请人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim ,  Seung Chul Lee

发明人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim ,  Seung Chul Lee

IPC分类号： H03M1/38

CPC分类号： H03M1/1245 ,  H03M1/002 ,  H03M1/44

摘要： Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC.

摘要翻译： 提供了没有前端采样保持放大器（SHA）的管线模数转换器（ADC）及其控制方法。 该方法包括以下步骤：在ADC和包括在第一级中的残余信号发生器同时对模拟输入信号进行采样，并分别产生第一采样值和第二采样值; 在剩余信号发生器处保持​​第二采样值，并且同时在ADC处放大并转换第一采样值为相应的数字代码; 以及在剩余信号发生器处产生使用数字码的残留信号。 流水线ADC和控制相同的方法最小化了通过去除前端SHA引起的采样失配，从而确保了没有前端SHA的稳定性能。 由于不使用前端SHA，因此可以减少芯片尺寸和功耗，并提高ADC的性能。

公开(公告)号：US07397409B2

公开(公告)日：2008-07-08

申请号：US11695143

申请日：2007-04-02

申请人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03M1/12

CPC分类号： H03M1/1225 ,  H03M1/168

摘要： A multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage and removing a sampling error of the input voltage; N-bit flash ADCs of first to K-th stages receiving analog signals, converting them into digital signals and outputting the digital signals; N-bit multiplying digital-to-analog converters (MDACs) of first to K-th stages converting differences between the digital signals output from the N-bit flash ADCs and output signals of preceding stages back into analog signals and outputting the analog signals; and a three-stage amplifier connected to an output of the N-bit MDAC of the first stage at a first clock and an output of the SHA at a second clock, wherein intergers N>= and K>=2. An amplifier can be shared between an SHA and an MDAC of a first stage, thereby reducing power consumption and chip size.In the multi-bit pipeline ADC, an amplifier can be shared between an SHA consuming much power and an MDAC of a first stage, so that power consumption and chip size can be reduced.

摘要翻译： 具有共享放大器结构的多位流水线模数转换器（ADC）包括：采样和保持放大器（SHA），用于采样和保持输入模拟电压并去除输入电压的采样误差; 第一至第K级的N位闪存ADC接收模拟信号，将其转换为数字信号并输出​​数字信号; 第一到第K级的N位乘法数模转换器（MDAC）将从N位闪存ADC输出的数字信号与前级的输出信号之间的差值转换成模拟信号并输出​​模拟信号; 以及三级放大器，在第一时钟连接到第一级的N位MDAC的输出，在第二时钟连接到SHA的输出，其中，间隔N> =且K> = 2。 放大器可以在第一级的SHA和MDAC之间共享，从而降低功耗和芯片尺寸。 在多位流水线ADC中，放大器可以在消耗大量功率的SHA和第一级的MDAC之间共享，从而可以降低功耗和芯片尺寸。

公开(公告)号：US07482966B2

公开(公告)日：2009-01-27

申请号：US11946583

申请日：2007-11-28

申请人： Seung Chul Lee ,  Young Deuk Jeon ,  Kwi Dong Kim ,  Jong Kee Kwon

发明人： Seung Chul Lee ,  Young Deuk Jeon ,  Kwi Dong Kim ,  Jong Kee Kwon

IPC分类号： H03M1/38

CPC分类号： H03M1/0678 ,  H03M1/162

摘要： Provided is an algorithm analog-to-digital converter (ADC). The algorithm ADC obtains two digital outputs through different capacitor connections for one analog input signal and adds the digital output signals to obtain a final output value, so that a mismatch factor of the capacitor is removed to minimize a linearity limitation resulting from the capacitor mismatch. In addition, the algorithm ADC minimizes power consumption by making the operating frequency slow at a cycle requiring a high resolution and making the operating frequency fast at a cycle requiring a low resolution, i.e., outputting different operating clock frequencies according to a required resolution.

摘要翻译： 提供了一种算法模数转换器（ADC）。 算法ADC通过不同的电容器连接获得两个数字输出，用于一个模拟输入信号，并将数字输出信号相加以获得最终输出值，从而消除电容器的失配因子，以最小化由电容器失配引起的线性限制。 此外，算法ADC通过使工作频率在需要高分辨率的周期中变慢，并使工作频率在需要低分辨率的周期（即，根据所需分辨率输出不同的工作时钟频率）的情况下将功率消耗最小化。

公开(公告)号：US07532146B2

公开(公告)日：2009-05-12

申请号：US11903476

申请日：2007-09-20

申请人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

发明人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

IPC分类号： H03M1/38

CPC分类号： H03M1/0682 ,  H03M1/167 ,  H03M1/804

摘要： Provided is a multi-bit pipeline analog-to-digital converter (ADC) having a merged capacitor switching structure. In a multiplying digital-to-analog converter (MDAC) used in the multi-bit pipeline ADC, switches are connected between the bottom plates of respective differential capacitors, thereby constantly maintaining a uniform input common mode voltage regardless of an input digital code. Thus, it is possible to improve the operating speed and performance of the MDAC.

摘要翻译： 提供了具有合并电容器开关结构的多位流水线模数转换器（ADC）。 在多位流水线ADC中使用的乘法数模转换器（MDAC）中，开关连接在各个差分电容器的底板之间，从而不管输入数字代码如何，始终保持均匀的输入共模电压。 因此，可以提高MDAC的操作速度和性能。

公开(公告)号：US20080129576A1

公开(公告)日：2008-06-05

申请号：US11903476

申请日：2007-09-20

申请人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

发明人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

IPC分类号： H03M1/14

CPC分类号： H03M1/0682 ,  H03M1/167 ,  H03M1/804

摘要： Provided is a multi-bit pipeline analog-to-digital converter (ADC) having a merged capacitor switching structure. In a multiplying digital-to-analog converter (MDAC) used in the multi-bit pipeline ADC, switches are connected between the bottom plates of respective differential capacitors, thereby constantly maintaining a uniform input common mode voltage regardless of an input digital code. Thus, it is possible to improve the operating speed and performance of the MDAC.

摘要翻译： 提供了具有合并电容器开关结构的多位流水线模数转换器（ADC）。 在多位流水线ADC中使用的乘法数模转换器（MDAC）中，开关连接在各个差分电容器的底板之间，从而不管输入数字代码如何，始终保持均匀的输入共模电压。 因此，可以提高MDAC的操作速度和性能。

公开(公告)号：US07486216B2

公开(公告)日：2009-02-03

申请号：US11707614

申请日：2007-02-16

申请人： Seung Chul Lee ,  Young Deuk Jeon ,  Kwi Dong Kim ,  Chong Ki Kwon

发明人： Seung Chul Lee ,  Young Deuk Jeon ,  Kwi Dong Kim ,  Chong Ki Kwon

IPC分类号： H03M1/38

CPC分类号： H03M1/002 ,  H03M1/007 ,  H03M1/069 ,  H03M1/168

摘要： Provided is a multi-bit pipeline analog-to-digital converter (ADC) capable of altering an operating mode. The ADC includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage; an n+1 number of B-bit flash ADCs for receiving an analog signal and converting the analog signal into a digital signal to output the digital signal; an n number of B-bit multiplying digital-to-analog converters (MDACs) for converting a difference between the digital signal output from the B-bit flash ADC and the front-stage output signal into an analog signal to output the analog signal to the next stage; and a mode control circuit for generating n-bit control signals to control the B-bit flash ADC and the B-bit MDAC according to required resolution and operating frequency. In the multi-bit pipeline ADC, an operating mode is altered by controlling the number of stages in a pipeline and a signal path according to required resolution and operating frequency, so that power consumption can be minimized under the corresponding operating condition and signals can be processed in a variety of ways.

摘要翻译： 提供了能够改变操作模式的多位流水线模数转换器（ADC）。 ADC包括：采样和保持放大器（SHA），用于采样和保持输入模拟电压; n + 1个B位闪存ADC，用于接收模拟信号并将模拟信号转换成数字信号以输出数字信号; 用于将从B位闪存ADC输出的数字信号与前级输出信号之间的差异转换为模拟信号的n个B位乘法数模转换器（MDAC），以将模拟信号输出到 下一阶段; 以及用于根据需要的分辨率和工作频率产生n位控制信号以控制B位闪存ADC和B位MDAC的模式控制电路。 在多位流水线ADC中，通过根据需要的分辨率和工作频率控制流水线中的级数和信号路径来改变操作模式，从而可以在相应的操作条件下使功耗最小化，信号可以是 以各种方式处理。

公开(公告)号：US20080129567A1

公开(公告)日：2008-06-05

申请号：US11707614

申请日：2007-02-16

申请人： Seung Chul Lee ,  Young Deuk Jeon ,  Kwi Dong Kim ,  Chong Ki Kwon

发明人： Seung Chul Lee ,  Young Deuk Jeon ,  Kwi Dong Kim ,  Chong Ki Kwon

IPC分类号： H03M1/14

CPC分类号： H03M1/002 ,  H03M1/007 ,  H03M1/069 ,  H03M1/168

摘要： Provided is a multi-bit pipeline analog-to-digital converter (ADC) capable of altering an operating mode. The ADC includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage; an n+1 number of B-bit flash ADCs for receiving an analog signal and converting the analog signal into a digital signal to output the digital signal; an n number of B-bit multiplying digital-to-analog converters (MDACs) for converting a difference between the digital signal output from the B-bit flash ADC and the front-stage output signal into an analog signal to output the analog signal to the next stage; and a mode control circuit for generating n-bit control signals to control the B-bit flash ADC and the B-bit MDAC according to required resolution and operating frequency. In the multi-bit pipeline ADC, an operating mode is altered by controlling the number of stages in a pipeline and a signal path according to required resolution and operating frequency, so that power consumption can be minimized under the corresponding operating condition and signals can be processed in a variety of ways.

摘要翻译： 提供了能够改变操作模式的多位流水线模数转换器（ADC）。 ADC包括：采样和保持放大器（SHA），用于采样和保持输入模拟电压; n + 1个B位闪存ADC，用于接收模拟信号并将模拟信号转换成数字信号以输出数字信号; 用于将从B位闪存ADC输出的数字信号与前级输出信号之间的差异转换为模拟信号的n个B位乘法数模转换器（MDAC），以将模拟信号输出到 下一阶段; 以及用于根据需要的分辨率和工作频率产生n位控制信号以控制B位闪存ADC和B位MDAC的模式控制电路。 在多位流水线ADC中，通过根据需要的分辨率和工作频率控制流水线中的级数和信号路径来改变操作模式，从而可以在相应的操作条件下使功耗最小化，信号可以 以各种方式处理。

公开(公告)号：US07705764B2

公开(公告)日：2010-04-27

申请号：US12198837

申请日：2008-08-26

申请人： Seung Chul Lee ,  Jae Won Nam ,  Young Deuk Jeon ,  Jong Kee Kwon

发明人： Seung Chul Lee ,  Jae Won Nam ,  Young Deuk Jeon ,  Jong Kee Kwon

IPC分类号： H03M1/12

CPC分类号： H03M1/1225 ,  H03M1/167

摘要： Provided are a method of algorithmic analog-to-digital conversion and an algorithmic Analog-to-Digital Converter (ADC). The algorithmic ADC includes a Multiplying Digital-to-Analog Converter (MDAC). The MDAC includes a Digital-to-Analog Converter (DAC) for converting a first digital signal into an analog signal, a subtractor for calculating a difference between the signal output from the DAC and an analog signal input from a first Sample and Hold Amplifier (SHA), an amplifier for amplifying the difference, a first capacitor unit connected with an output end of the first SHA and an input end of the amplifier through a first switching unit, a second capacitor unit connected with the input end and an output end of the amplifier through a second switching unit, and a third capacitor unit connected with the input end and the output end of the amplifier through a third switching unit.

摘要翻译： 提供了一种算法模数转换方法和算法模数转换器（ADC）。 该算法ADC包括一个乘法数字模拟转换器（MDAC）。 MDAC包括用于将第一数字信号转换为模拟信号的数模转换器（DAC），减法器，用于计算从DAC输出的信号与从第一采样和保持放大器输入的模拟信号之间的差值 SHA），用于放大差分的放大器，通过第一开关单元与第一SHA的输出端连接的第一电容器单元和放大器的输入端，与输入端连接的第二电容器单元和输出端 通过第二开关单元的放大器，以及通过第三开关单元与放大器的输入端和输出端连接的第三电容器单元。

公开(公告)号：US06608578B2

公开(公告)日：2003-08-19

申请号：US10032720

申请日：2001-12-27

申请人： Seung Chul Lee ,  Jong Kee Kwon ,  Kwi Dong Kim ,  Kyung Soo Kim

发明人： Seung Chul Lee ,  Jong Kee Kwon ,  Kwi Dong Kim ,  Kyung Soo Kim

IPC分类号： H03M166

CPC分类号： H03K17/102 ,  H03K17/04106 ,  H03M1/742

摘要： The present invention relates to a current cell driving circuit in a digital-to-analog converter. The current cell driving circuit limits the potential of differential control signals to a given potential level by means of a voltage limiter using a parasitic capacitance of a transistor. Therefore, the present invention can effectively limit the potential of differential control signals DP and DN without compromising the power consumption and the circuit area and also can minimize the transfer time.

摘要翻译： 本发明涉及数模转换器中的电流单元驱动电路。 当前单元驱动电路通过使用晶体管的寄生电容的限压器将差分控制信号的电位限制到给定电位电平。 因此，本发明可以有效地限制差分控制信号DP和DN的潜力，而不损害功耗和电路面积，并且还可以最小化传送时间。