公开(公告)号：US20070065959A1

公开(公告)日：2007-03-22

申请号：US11273382

申请日：2005-11-12

申请人： Yu-Ju Chang ,  Jui-Hsiang Yen ,  Chi-Meng Lu ,  Tse-Liang Ying

发明人： Yu-Ju Chang ,  Jui-Hsiang Yen ,  Chi-Meng Lu ,  Tse-Liang Ying

IPC分类号： H01L21/00

CPC分类号： H01L33/02 ,  H01L33/20 ,  H01L33/42

摘要： A method for manufacturing a light-emitting diode is described, comprising the following steps. A substrate is provided. An illuminant epitaxial structure is formed on the substrate, wherein the illuminant epitaxial structure comprises a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer stacked on the substrate in sequence, a surface of the second conductivity type semiconductor layer includes at least one epitaxial defect formed therein, and the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are opposite conductivity types. Then, an insulation layer is formed to fill into the epitaxial defect in the second conductivity type semiconductor layer. A transparent electrode layer is formed on the surface of the second conductivity type semiconductor layer.

摘要翻译： 描述了一种用于制造发光二极管的方法，包括以下步骤。 提供基板。 在基板上形成发光体外延结构，其中，所述发光体外延结构依次包括在所述基板上堆叠的第一导电型半导体层，有源层和第二导电型半导体层，所述第二导电型半导体层的表面包括 其中形成有至少一个外延缺陷，并且第一导电类型半导体层和第二导电类型半导体层是相反的导电类型。 然后，形成绝缘层以填充第二导电类型半导体层中的外延缺陷。 在第二导电型半导体层的表面上形成透明电极层。

公开(公告)号：US06433665B1

公开(公告)日：2002-08-13

申请号：US09839702

申请日：2001-04-23

申请人： Kuo-Ching Huang ,  Jin Yuan Lee ,  Tse-Liang Ying

发明人： Kuo-Ching Huang ,  Jin Yuan Lee ,  Tse-Liang Ying

IPC分类号： H01F500

摘要： An improved thin film inductor design is described. A spiral geometry is used to which has been added a core of high permeability material located at the center of the spiral. If the high permeability material is a conductor, care must be taken to avoid any contact between the core and the spiral. If a dielectric ferromagnetic material is used, this constraint is removed from the design. Several other embodiments are shown in which, in addition to the high permeability core, provide low reluctance paths for the structure. In one case this takes the form of a frame of ferromagnetic material surrounding the spiral while in a second case it has the form of a hollow square located directly above the spiral.

公开(公告)号：US06278352B1

公开(公告)日：2001-08-21

申请号：US09359892

申请日：1999-07-26

申请人： Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

发明人： Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

IPC分类号： H01F500

CPC分类号： H01F5/003

摘要： An improved thin film inductor design is described. A spiral geometry is used to which has been added a core of high permeability material located at the center of the spiral. If the high permeability material is a conductor, care must be taken to avoid any contact between the core and the spiral. If a dielectric ferromagnetic material is used, this constraint is removed from the design. Several other embodiments are shown in which, in addition to the high permeability core, provide low reluctance paths for the structure. In one case this takes the form of a frame of ferromagnetic material surrounding the spiral while in a second case it has the form of a hollow square located directly above the spiral.

摘要翻译： 描述了改进的薄膜电感器设计。 使用螺旋几何形状，其中已经添加了位于螺旋中心的高磁导率材料的核心。 如果高导磁率材料是导体，则必须注意避免芯和螺旋之间的任何接触。 如果使用介电铁磁材料，则从设计中去除该约束。 示出了其中除了高磁导率芯之外还提供用于结构的低磁阻路径的其它实施例。 在一种情况下，这采取围绕螺旋的铁磁材料框架的形式，而在第二种情况下，其具有直接位于螺旋上方的中空正方形的形式。

公开(公告)号：US5885865A

公开(公告)日：1999-03-23

申请号：US851689

申请日：1997-05-06

申请人： Mong-Song Liang ,  Julie Huang ,  Tse-Liang Ying ,  Chen-Jong Wang

发明人： Mong-Song Liang ,  Julie Huang ,  Tse-Liang Ying ,  Chen-Jong Wang

IPC分类号： E04G23/02 ,  E04B1/64 ,  H01L21/8242

CPC分类号： E04B1/648

摘要： The present invention discloses a method for making low-topography buried capacitor including the steps of first depositing oxide layers, and then forming a small pre-contact hole by a dry etch method and a large contact hole by a wet etch method while using silicon nitride caps and sidewall spacers previously deposited on the word lines and on the bit lines as etch stop layers. A buried capacitor that has significantly improved topography can be fabricated in a semiconductor device.

摘要翻译： 本发明公开了一种制备低地埋式电容器的方法，包括以下步骤：首先沉积氧化物层，然后通过干蚀刻法和大型接触孔通过湿法蚀刻法形成小预接触孔，同时使用氮化硅 预先沉积在字线和位线上的帽和侧壁间隔作为蚀刻停止层。 可以在半导体器件中制造具有显着改善的形貌的埋电容器。

公开(公告)号：US5753547A

公开(公告)日：1998-05-19

申请号：US789238

申请日：1997-01-28

申请人： Tse-Liang Ying

发明人： Tse-Liang Ying

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： The present invention provides a method of manufacturing a stacked cylindrical capacitor having a smooth top cylindrical surface and uniform height. A first insulating layer 20 is formed over the substrate 10. A barrier layer 22 having an opening 23 is formed over a first insulating layer 20 on a substrate. A second insulating layer 24 composed of silicon oxide is formed on the barrier layer 22. The second insulating layer 24 and the first insulating layer 20 are patterned forming a first cylindrical opening 26 exposing the active region of the substrate 10 and forming a second cylindrical opening 30 in the second insulating layer 24 that exposes portions of the barrier layer 22. A conformal polysilicon layer 34 is formed over the resultant surface and the walls of the cylindrical openings 26 30. A planarizing layer 36 is formed over the resulting surface and then etched back forming a planarizing plug 36A that partially fills the second cylindrical opening 30A. A third insulation layer 40 is formed over resultant surface. The third insulating layer 40 and the polysilicon layer 34 are isotropically etched back forming a cylindrical bottom electrode 44 with a smooth top surface 44A. The smooth top electrode surface 44A increases the breakdown voltage to the capacitor.

摘要翻译： 本发明提供一种制造具有平滑顶部圆柱形表面和均匀高度的层叠圆柱形电容器的方法。 第一绝缘层20形成在衬底10上。具有开口23的阻挡层22形成在衬底上的第一绝缘层20上。 在阻挡层22上形成由氧化硅构成的第二绝缘层24.对第二绝缘层24和第一绝缘层20进行图案化，形成露出基板10的有源区的第一圆柱形开口26，并形成第二圆柱形开口 在第二绝缘层24中暴露出阻挡层22的一部分。在合成的表面和圆柱形开口26,30的壁上形成共形多晶硅层34.平坦化层36形成在所得表面上，然后蚀刻 后部形成部分填充第二圆柱形开口30A的平坦化塞子36A。 在合成表面上形成第三绝缘层40。 第三绝缘层40和多晶硅层34被各向同性地回蚀，形成具有光滑顶表面44A的圆柱形底电极44。 光滑的顶部电极表面44A增加了对电容器的击穿电压。

公开(公告)号：US06373369B2

公开(公告)日：2002-04-16

申请号：US09839927

申请日：2001-04-23

申请人： Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

发明人： Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

IPC分类号： H01F500

CPC分类号： H01F5/003

摘要： An improved thin film inductor design is described. A spiral geometry is used to which has been added a core of high permeability material located at the center of the spiral. If the high permeability material is a conductor, care must be taken to avoid any contact between the core and the spiral. If a dielectric ferromagnetic material is used, this constraint is removed from the design. Several other embodiments are shown in which, in addition to the high permeability core, provide low reluctance paths for the structure. In one case this takes the form of a frame of ferromagnetic material surrounding the spiral while in a second case it has the form of a hollow square located directly above the spiral.

摘要翻译： 描述了改进的薄膜电感器设计。 使用螺旋几何形状，其中已经添加了位于螺旋中心的高磁导率材料的核心。 如果高导磁率材料是导体，则必须注意避免芯和螺旋之间的任何接触。 如果使用介电铁磁材料，则从设计中去除该约束。 示出了其中除了高磁导率芯之外还提供用于结构的低磁阻路径的其它实施例。 在一种情况下，这采取围绕螺旋的铁磁材料框架的形式，而在第二种情况下，其具有直接位于螺旋上方的中空正方形的形式。

公开(公告)号：US06287939B1

公开(公告)日：2001-09-11

申请号：US09216789

申请日：1998-12-21

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/76895

摘要： The invention provides a method for fabricating a shallow trench isolation which is not susceptable to buried contact trench formation. The invention also provides immunity from the STI “kink effect,” as well as benefits associated with nitridation. The process begins by forming a pad oxide layer on a semiconductor substrate. A nitride layer is formed on the pad oxide layer. The nitride layer, the pad oxide layer, and the semiconductor substrate are patterned to form trenches. Next, a fill oxide layer is formed over the nitride layer, the pad oxide layer, and the semiconductor substrate. The fill oxide layer is chemical-mechanical polished, stopping on the nitride layer to form fill oxide regions. N2 ions are implanted into the fill oxide regions. An anneal is performed to form a buried oxynitride layer. The buried oxynitride layer is partially above the level of the top surface of the semiconductor substrate and partially below the level of the top surface of the semiconductor substrate. The nitride layer is removed. Then, the pad oxide layer and portions of the fill oxide regions are removed using the buried oxynitride layer as an etch stop, forming shallow trench isolations.

摘要翻译： 本发明提供一种用于制造不易于埋入接触沟槽形成的浅沟槽隔离的方法。 本发明还提供了对STI“扭结效应”的免疫力以及与氮化相关的益处。 该过程开始于在半导体衬底上形成衬垫氧化物层。 在衬垫氧化物层上形成氮化物层。 图案化氮化物层，衬垫氧化物层和半导体衬底以形成沟槽。 接下来，在氮化物层，衬垫氧化物层和半导体衬底之上形成填充氧化物层。 填充氧化物层进行化学机械抛光，在氮化物层上停止形成填充氧化物区域。 将N 2离子注入填充氧化物区域。 进行退火以形成掩埋的氮氧化物层。 掩埋的氧氮化物层部分地高于半导体衬底的顶表面的高度，并且部分地低于半导体衬底的顶表面的水平。 去除氮化物层。 然后，使用掩埋氧氮化物层作为蚀刻停止层，去除衬垫氧化物层和填充氧化物区域的部分，形成浅沟槽隔离。

公开(公告)号：US06214715B1

公开(公告)日：2001-04-10

申请号：US09349841

申请日：1999-07-08

申请人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

发明人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

IPC分类号： H01L2144

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10885 ,  H01L28/91 ,  H01L28/92

摘要： This invention provides a method for forming a self aligned contact without key holes using a two step sidewall spacer deposition. The process begins by providing a semiconductor structure having a device layer, a first inter poly oxide layer (IPO-1), and a conductive structure (such as a bit line) thereover, and having a contact area on the device layer adjacent to the conductive structure. The semiconductor structure can further include an optional etch stop layer overlying the first inter poly oxide layer. The conductive structure comprises at least one conductive layer with a hard mask thereover. A first spacer layer is formed over the hard mask and the IPO-1 layer and anisotropically etched to form first sidewall spacers on the sidewalls of the conductive structure up to a level above the bottom of the hard mask and below the level of the top of the hard mask such that the profile of the first sidewall spacers are not concave at any point. A second spacer layer is formed over the first sidewall spacers and anisotropically etched to form second sidewall spacers, having a profile that is not concave at any point. A second inter poly oxide layer is formed over the second sidewall spacers, the hard mask, and the IPO-1 layer, whereby the second inter poly oxide layer is free from key holes. A contact opening is formed in the second inter poly oxide layer and the first inter poly oxide layer over the contact area. A contact plug is formed in the contact openings.

摘要翻译： 本发明提供一种用于使用两步侧壁间隔物沉积形成无键孔的自对准接触的方法。 该过程开始于提供具有器件层，第一多晶硅氧化物层（IPO-1）和导电结构（例如位线）的半导体结构，并且在与其相邻的器件层上具有接触区域 导电结构。 半导体结构还可以包括覆盖在第一多晶硅氧化物层上的任选的蚀刻停止层。 导电结构包括至少一个具有硬掩模的导电层。 在硬掩模和IPO-1层上形成第一间隔层，并且各向异性蚀刻以在导电结构的侧壁上形成直到硬掩模的底部以上的水平并且低于 硬掩模，使得第一侧壁隔片的轮廓在任何点都不是凹的。 第二间隔层形成在第一侧壁间隔物上并且各向异性蚀刻以形成第二侧壁间隔物，其具有在任何点处不凹的轮廓。 在第二侧壁间隔物，硬掩模和IPO-1层上形成第二多晶硅氧化物层，由此第二多晶氧化物层没有键孔。 在接触区域上的第二多晶氧化物层和第一多晶氧化物层中形成接触开口。 在接触开口中形成接触塞。

公开(公告)号：US6080637A

公开(公告)日：2000-06-27

申请号：US206736

申请日：1998-12-07

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Yeh Shih

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Yeh Shih

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224 ,  Y10S148/05

摘要： A process for creating an insulator filled, shallow trench, in a semiconductor substrate, in which the insulator layer in the shallow trench, is not exposed to procedures used to remove defining composite insulator layers, has been developed. The process features creating a lateral recess, in a thick silicon nitride layer, used as a component of a composite insulator layer, where the composite insulator layer is used for subsequent definition of the shallow trench, in the semiconductor substrate. An insulator deposition, filling openings, and recesses, in the composite insulator layer, and filling the shallow trench, followed by removal of excess insulator fill, on the top surface of the composite insulator layer, results in the formation of a "T" shape insulator, comprised of an insulator shape, in the shallow trench, and comprised of a wider insulator shape, located in the composite insulator shape, with the lateral recess in the thick silicon nitride layer, and with the wider insulator shape, overlying the narrow, insulator shape, in the shallow trench. The insulator, in the shallow trench, is protected from the procedure used to remove components of the composite insulator layer, by the wider insulator shape.

摘要翻译： 已经开发了在半导体衬底中形成绝缘体填充的浅沟槽的方法，其中浅沟槽中的绝缘体层不暴露于用于移除限定复合绝缘体层的程序。 该工艺的特征是在半导体衬底中产生在厚氮化硅层中用作复合绝缘体层的组分的横向凹槽，其中复合绝缘体层用于随后定义浅沟槽。 在复合绝缘体层中的绝缘体沉积，填充开口和凹陷，以及填充浅沟槽，然后在复合绝缘体层的顶表面上除去多余的绝缘体填充物，导致形成“T”形 绝缘体，由绝缘体形状构成，位于浅沟槽中，并且由更宽的绝缘体形状组成，位于复合绝缘体形状中，侧壁凹陷在厚氮化硅层中，并且具有更宽的绝缘体形状， 绝缘体形状，在浅沟槽。 通过更宽的绝缘体形状，在浅沟槽中的绝缘体被保护以避免用于去除复合绝缘体层的部件的程序。

公开(公告)号：US5946596A

公开(公告)日：1999-08-31

申请号：US734624

申请日：1996-10-18

申请人： Tse-Liang Ying

发明人： Tse-Liang Ying

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/32053 ,  H01L21/76819

摘要： The present invention provides a method for preventing a polycide line situated between two dielectric layers from deformation during a reflow process for one of the dielectric layers by annealing the polycide line and thereby increasing its hardness prior to the reflow process being conducted. The annealing process can be carried out either before or after the polycide line is formed at an annealing temperature in the range between about 700.degree. C. and about 1000.degree. C. in a furnace or by a rapid thermal process.

摘要翻译： 本发明提供了一种防止位于两个电介质层之间的多硅化物线在电介质层的回流工艺期间通过退火多孔线而变形，从而在进行回流工艺之前增加其硬度的方法。 在退火温度范围为700〜1000℃的快速热处理之前或之后，可以进行退火处理。