CLASS-D AUDIO AMPLIFIER AND NOISE ELIMINATION DEVICE THEREOF

    公开(公告)号:US20250150038A1

    公开(公告)日:2025-05-08

    申请号:US18387091

    申请日:2023-11-06

    Abstract: A noise elimination device for a Class-D audio amplifier includes a residual signal detector and a multiplexer, wherein the multiplexer is electrically connected with a sigma-delta modulator (SDM) and a pulse width modulator (PWM) of the Class-D audio amplifier and the residual signal detector. The residual signal detector is configured to detect whether an input signal of the Class-D audio amplifier is residual. The multiplexer is configured to output zero data into the pulse width modulator when the residual signal detector detects that the input signal of the Class-D audio amplifier is residual.

    Electronic device and method for audio signal processing

    公开(公告)号:US12267072B2

    公开(公告)日:2025-04-01

    申请号:US18125331

    申请日:2023-03-23

    Abstract: An electronic device includes a sampling circuit and a summing circuit coupled with the sampling circuit. The sampling circuit samples a pulse width of a first input pulse of a PWM input signal since a first time point on a rising edge of a clock pulse of a clock signal. The summing circuit generates a first output pulse of a PWM output signal since a second time point on a falling edge of the clock pulse. A pulse width of the first output pulse is a summation of the pulse width of the first input pulse and a pulse width of a second input pulse of the PWM input signal, and the second input pulse is the next pulse after the first input pulse.

    Voltage mode controlled linear frequency modulation oscillator

    公开(公告)号:US12191809B2

    公开(公告)日:2025-01-07

    申请号:US18326034

    申请日:2023-05-31

    Inventor: Yao-Wei Yang

    Abstract: A voltage mode controlled linear frequency modulation oscillator comprises a voltage modulation circuit, a reference current generating circuit, and an oscillating circuit. The voltage modulation circuit is configured to generate a modulation voltage according to a feedback voltage and a first reference voltage. The reference current generating circuit, coupled to the voltage modulation circuit, is configured to generate a first reference current according to the modulation voltage and a second reference voltage. The oscillating circuit, coupled to the reference current generating circuit, is configured to generate an oscillating signal with an oscillating frequency according to the first reference current, wherein the oscillating frequency varies with the modulation voltage.

    CHARGER CIRCUIT WITH THERMAL REGULATION
    4.
    发明公开

    公开(公告)号:US20240186813A1

    公开(公告)日:2024-06-06

    申请号:US18073593

    申请日:2022-12-02

    Inventor: YAO-WEI YANG

    CPC classification number: H02J7/007192 H02J7/00309 H02J7/0047

    Abstract: A charger circuit comprises a constant current charging circuit and a thermal regulation circuit. The constant current charging circuit is configured for generating a charging current, including a charger input terminal for receiving an input voltage, a charge current setting terminal, a charger output terminal for outputting the charging current, a current mirror including a reference current path between the charger input terminal and charge current setting terminal and an output current path between the charger input terminal and charger output terminal, and a feedback amplifier having a positive terminal, a negative terminal for receiving a feedback reference voltage, and a feedback output terminal coupled to the current mirror. The thermal regulation circuit is configured for generating and modulating a thermal regulation voltage with temperature, and outputting the thermal regulation voltage across the positive terminal of the feedback amplifier and the charging current setting terminal.

    IC DIE FORMING METHOD AND IC DIE STRUCTURE
    5.
    发明公开

    公开(公告)号:US20230387004A1

    公开(公告)日:2023-11-30

    申请号:US17826141

    申请日:2022-05-26

    CPC classification number: H01L23/528 H01L21/82 H03K17/08

    Abstract: An integrated circuit die forming method, for forming a plurality of integrated circuit dies on a semiconductor wafer, comprising: forming a first device, a second device in a first die in a first area; forming a metal layer connected to the first device and the second device; forming a third device, a fourth device in a second die in a second area; forming the metal layer connected to the third device and the fourth device, wherein a scribe area exists between the first area and the second area is separated by; wherein the first device and the third device are used for synchronization and are components of a class D amplifier; wherein the second device is used for preventing leakage currents of the first die and the fourth device is used for preventing leakage currents of the second die.

    Control circuit of brushless direct current motor and method for detecting initial rotor position of brushless direct current motor

    公开(公告)号:US11750123B1

    公开(公告)日:2023-09-05

    申请号:US17841699

    申请日:2022-06-16

    Inventor: Ming-Fu Tsai

    CPC classification number: H02P6/182 H02P6/20 H02P2203/03

    Abstract: A control circuit arranged to detect an initial rotor position of a brushless DC motor includes: a voltage integrator circuit, arranged to perform integration upon an input voltage, to generate a plurality of integrated voltages; a PWM generating circuit, arranged to generate and output a plurality of PWM signals to the brushless DC motor through a drive circuit, and stop outputting a PWM signal that is any of the plurality of PWM signals to the brushless DC motor according to an integrated voltage corresponding to the PWM signal; a current receiving circuit, arranged to receive a plurality of feedback currents from the brushless DC motor; a comparison circuit, arranged to perform comparison upon the plurality of feedback currents, to generate a comparison result; and a decision circuit, arranged to detect the initial rotor position according to the comparison result.

    Apparatus for noise reduction in audio signal processing

    公开(公告)号:US11699423B1

    公开(公告)日:2023-07-11

    申请号:US17583235

    申请日:2022-01-25

    CPC classification number: G10K11/17813 H03G3/001

    Abstract: An apparatus for noise reduction in audio signal processing includes a power amplifier, a zero-crossing detector, and a threshold detector. The power amplifier has an input signal terminal for receiving an audio input signal and an output signal terminal. The audio input signal is a digital-to-analog converted version according to a version of a digital audio signal. The power amplifier has an analog gain which is controllable in response to an analog gain control signal. The zero-crossing detector determines a zero-crossing detection signal according to an internal signal provided between the input signal terminal and the output signal terminal. The threshold detector determines a gain setting according to the digital audio signal and the zero-crossing detection signal to generate the analog gain control signal indicating the gain setting, wherein the threshold detector controls the analog gain of the power amplifier according to the analog gain control signal.

    Comparator circuit with dynamic biasing

    公开(公告)号:US11626868B1

    公开(公告)日:2023-04-11

    申请号:US17585605

    申请日:2022-01-27

    Inventor: Yao-Ren Chang

    Abstract: A comparator circuit with dynamic biasing comprises a comparator, first dynamic biasing generator, first extra biasing device, second dynamic biasing generator, and second extra biasing device. The comparator includes a biasing circuit, input stage, active loads, and output terminal. The input stage has a first input terminal, second input terminal, first current path, and second current path. The comparator is configured to output an output signal at the output terminal according to the first input signal and second input signal. The first dynamic biasing generator is coupled between a first detection node and the first extra biasing device coupled to the biasing circuit. The second dynamic biasing generator is coupled between a second detection node and the second extra biasing device coupled to the biasing circuit. The first and second detection nodes are between the input stage and the active loads.

    Amplifier and LPDDR3 input buffer
    10.
    发明授权

    公开(公告)号:US11514975B2

    公开(公告)日:2022-11-29

    申请号:US17206090

    申请日:2021-03-18

    Inventor: Shu-Han Nien

    Abstract: An amplifier with an input stage comprising: a first current mirror; a first input differential pair; a first current source; a second current source; a second input differential pair, wherein the first input differential pair and the second input differential pair receive a reference voltage; a second current mirror; and a voltage control transmission circuit. An extra current path in the first current mirror is formed and a current flowing through the extra current path flows through the second current mirror to a ground when the reference voltage is higher than a first predetermined value. Also, an extra current path in the second current mirror is formed and a current flowing through the extra current path in the second current mirror flows to the first current mirror when the reference voltage is lower than a second predetermined value.

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