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公开(公告)号：US20250157515A1
公开(公告)日：2025-05-15
申请号：US18509318
申请日：2023-11-15
Applicant: Faraday Technology Corp.
Inventor： Sivaramakrishnan Subramanian , Hussainvali Shaik , Eswar Reddi
Abstract: A memory apparatus includes a DFE receiver and a DFE reset circuit. The DFE receiver is configured to receive a data signal and a data strobe signal from a memory device. The DFE receiver includes a DFE tap that is determined according to a previous data signal, and the DFE receiver adjusts the data signal according to the DFE tap. The DFE reset circuit is configured to receive a gate enable signal and an internal enable signal from the memory controller, generate a DFE reset signal according to the gate enable signal and the internal enable signal. The DFE reset circuit outputs the DFE reset signal to the DFE receiver to reset the DFE tap of the DFE receiver between read bursts.
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公开(公告)号：US20250125806A1
公开(公告)日：2025-04-17
申请号：US18380635
申请日：2023-10-16
Applicant: Faraday Technology Corp.
Inventor： Mikhail Tamrazyan , Vinod Kumar Jain
Abstract: A clock and data recovery (CDR) circuit includes: a frequency tracking loop including an injection locked oscillator for adjusting a frequency of oscillation to generate an output signal having a frequency tracked to a reference clock frequency, and then receiving an input data signal and extracting an output clock from the input data signal; and a phase tracking circuit coupled to the frequency tracking loop. The phase tracking circuit includes: a phase interpolator for receiving the output clock and adjusting a phase of the output clock according to an input code to generate a sampling clock for sampling a signal to generate a deserialized signal; and a finite state machine, coupled to the phase interpolator, for outputting a code to the phase interpolator according to the deserialized signal of the multiplexer in order to adjust the phase of the output clock.
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公开(公告)号：US12278639B1
公开(公告)日：2025-04-15
申请号：US18380635
申请日：2023-10-16
Applicant: Faraday Technology Corp.
Inventor： Mikhail Tamrazyan , Vinod Kumar Jain
Abstract: A clock and data recovery (CDR) circuit includes: a frequency tracking loop including an injection locked oscillator for adjusting a frequency of oscillation to generate an output signal having a frequency tracked to a reference clock frequency, and then receiving an input data signal and extracting an output clock from the input data signal; and a phase tracking circuit coupled to the frequency tracking loop. The phase tracking circuit includes: a phase interpolator for receiving the output clock and adjusting a phase of the output clock according to an input code to generate a sampling clock for sampling a signal to generate a deserialized signal; and a finite state machine, coupled to the phase interpolator, for outputting a code to the phase interpolator according to the deserialized signal of the multiplexer in order to adjust the phase of the output clock.
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公开(公告)号：US12266412B2
公开(公告)日：2025-04-01
申请号：US18323430
申请日：2023-05-25
Applicant: Faraday Technology Corp.
Inventor： Yi-Hsin Tseng , Chi-Chang Shuai , Yen-Yao Wang
Abstract: A content addressable memory (CAM) and a CAM cell are provided. The CAM includes a memory cell array and a disabling circuit. The memory cell array includes a plurality of CAM cells, wherein each of the CAM cells includes a memory cell circuit and a comparison circuit. When the CAM cells in a first column of the memory cell array are normal, the disabling circuit enables the comparison circuits of the CAM cells in the first column, so that the comparison circuits in the first column respectively present the comparison results on different match lines. When any one of the CAM cells in the first column is defective, the disabling circuit disables the comparison circuits of the CAM cells in the first column, so that the disabled comparison circuits does not affect the different match lines.
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公开(公告)号：US20240370204A1
公开(公告)日：2024-11-07
申请号：US18361923
申请日：2023-07-31
Applicant: Faraday Technology Corp.
Inventor： Chang-Chin Chung , Shen-Chang Wang
IPC: G06F3/06
Abstract: A command reorder device with a retry function and an operation method thereof are provided. The command reorder device includes a first switch circuit, multiple command buffers, a second switch circuit, and a queue control circuit. The queue control circuit controls the first switch circuit to push an input command of an input command string to a first command buffer. The queue control circuit controls the second switch circuit to pop out an output command from a second command buffer based on a programmable reorder policy. The queue control circuit checks whether an error notification is received during a monitoring period from when the output command is popped out from the second command buffer. According to the check result, the queue control circuit determines either to pop out the output command from the second command buffer again, or to release the memory space of the second command buffer.
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Patent Agency Ranking
公开(公告)号：US20240355408A1
公开(公告)日：2024-10-24
申请号：US18323430
申请日：2023-05-25
Applicant: Faraday Technology Corp.
Inventor： Yi-Hsin Tseng , Chi-Chang Shuai , Yen-Yao Wang
CPC classification number: G11C29/4401 , G11C15/04
Abstract: A content addressable memory (CAM) and a CAM cell are provided. The CAM includes a memory cell array and a disabling circuit. The memory cell array includes a plurality of CAM cells, wherein each of the CAM cells includes a memory cell circuit and a comparison circuit. When the CAM cells in a first column of the memory cell array are normal, the disabling circuit enables the comparison circuits of the CAM cells in the first column, so that the comparison circuits in the first column respectively present the comparison results on different match lines. When any one of the CAM cells in the first column is defective, the disabling circuit disables the comparison circuits of the CAM cells in the first column, so that the disabled comparison circuits does not affect the different match lines.
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公开(公告)号：US20240178753A1
公开(公告)日：2024-05-30
申请号：US18135182
申请日：2023-04-16
Applicant: Faraday Technology Corp.
Inventor： Chen-Hui Xu , Xiao-Dong Fei , Wen-Chi Huang , Hui-Wen Hu
IPC: H02M3/155
CPC classification number: H02M3/155
Abstract: The present invention discloses a regulator. The regulator includes a bias voltage generating circuit and a flipped voltage follower (FVF), wherein the bias voltage generating circuit is configured to generate a bias voltage, and the FVF is configured to generate an output voltage according to the bias voltage and a supply voltage. The FVF includes a first P-type transistor and a first N-type transistor. The P-type transistor is configured to receive the bias voltage via a gate electrode of the P-type transistor, to generate the output voltage on a source electrode of the P-type transistor. A drain electrode of the first N-type transistor is connected to the supply voltage, a source electrode of the first N-type transistor is connected to the source electrode of the first P-type transistor, and a gate electrode of the first N-type transistor receives a driving signal for compensating the output voltage.
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8.发明授权公开(公告)号：US11855710B2
公开(公告)日：2023-12-26
申请号：US17191655
申请日：2021-03-03
Applicant: Faraday Technology Corp.
Inventor： Chia Jung Chan , Wei-Cyuan Wu
IPC: H04B3/23
CPC classification number: H04B3/231
Abstract: An echo cancellation device and an echo cancellation method thereof applied in a communication device are provided. The echo cancellation device includes an echo canceller and a combine circuit. The echo canceller obtains a plurality of delayed signals from a local signal of the communication device, and the delayed signals are divided into a plurality of delayed signal groups. The echo canceller selectively ignores at least one of the delayed signal groups, and the echo canceller generates an echo cancellation signal with the others of the delayed signal groups. The combine circuit is coupled to an interface circuit of the communication device to receive a received signal. The combine circuit cancels an echo component of the received signal with the echo cancellation signal to generate a cancelled signal.
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公开(公告)号：US20230163740A1
公开(公告)日：2023-05-25
申请号：US17531811
申请日：2021-11-22
Applicant: Faraday Technology Corp.
Inventor： PRATEEK KUMAR GOYAL , RAGHU NANDAN CHEPURI , VINOD KUMAR JAIN
CPC classification number: H03G3/3084 , H03F3/45 , H03M1/12 , H04B10/6933 , H03F2200/375 , H03F2203/45212
Abstract: A method for removing offset in a receiver of an integrated circuit (IC) includes: determining digital codes of differential input voltages of an amplifier in a first receiving lane of the receiver; comparing the digital codes to a digital code corresponding to an optimum common mode voltage (VCM) of the receiver; according to the comparison, determining a bias code for adjusting both the differential input voltages to match the optimum VCM; and inputting the bias code to a bias circuit of the receiver. The first receiving lane of the receiver includes a plurality of amplifiers. The method steps are repeated for each amplifier of the plurality of amplifiers, and then repeated for all receiving lanes of the IC.
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10.发明授权公开(公告)号：US11381222B2
公开(公告)日：2022-07-05
申请号：US17178194
申请日：2021-02-17
Applicant: FARADAY TECHNOLOGY CORPORATION , Faraday Technology Corp.
Inventor： Ling Chen , Andrew Chao , Xiao-Dong Fei
Abstract: An apparatus for performing baseline wander correction (BLWC) with the aid of differential wander current sensing includes filters and a correction circuit. The filters are positioned in a front-end circuit of a receiver and coupled to a set of input terminals of the receiver, and filter a set of input signals on the set of input terminals to generate a set of differential signals on a set of secondary terminals, for further usage by the receiver. The correction circuit is positioned in the frontend circuit and electrically connected to the set of input terminals and the set of secondary terminals, and performs BLWC on the set of differential signals according to the set of input signals. In the correction circuit, amplifiers and resistors form a differential wander current sensor to sense differential wander current, and a set of current mirrors generate corresponding baseline wander compensation current to perform BLWC.
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