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公开(公告)号：US20240355408A1
公开(公告)日：2024-10-24
申请号：US18323430
申请日：2023-05-25
发明人： Yi-Hsin Tseng , Chi-Chang Shuai , Yen-Yao Wang
CPC分类号： G11C29/4401 , G11C15/04
摘要： A content addressable memory (CAM) and a CAM cell are provided. The CAM includes a memory cell array and a disabling circuit. The memory cell array includes a plurality of CAM cells, wherein each of the CAM cells includes a memory cell circuit and a comparison circuit. When the CAM cells in a first column of the memory cell array are normal, the disabling circuit enables the comparison circuits of the CAM cells in the first column, so that the comparison circuits in the first column respectively present the comparison results on different match lines. When any one of the CAM cells in the first column is defective, the disabling circuit disables the comparison circuits of the CAM cells in the first column, so that the disabled comparison circuits does not affect the different match lines.
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公开(公告)号：US20240178753A1
公开(公告)日：2024-05-30
申请号：US18135182
申请日：2023-04-16
发明人： Chen-Hui Xu , Xiao-Dong Fei , Wen-Chi Huang , Hui-Wen Hu
IPC分类号： H02M3/155
CPC分类号： H02M3/155
摘要： The present invention discloses a regulator. The regulator includes a bias voltage generating circuit and a flipped voltage follower (FVF), wherein the bias voltage generating circuit is configured to generate a bias voltage, and the FVF is configured to generate an output voltage according to the bias voltage and a supply voltage. The FVF includes a first P-type transistor and a first N-type transistor. The P-type transistor is configured to receive the bias voltage via a gate electrode of the P-type transistor, to generate the output voltage on a source electrode of the P-type transistor. A drain electrode of the first N-type transistor is connected to the supply voltage, a source electrode of the first N-type transistor is connected to the source electrode of the first P-type transistor, and a gate electrode of the first N-type transistor receives a driving signal for compensating the output voltage.
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3.发明授权公开(公告)号：US11855710B2
公开(公告)日：2023-12-26
申请号：US17191655
申请日：2021-03-03
发明人： Chia Jung Chan , Wei-Cyuan Wu
IPC分类号： H04B3/23
CPC分类号： H04B3/231
摘要： An echo cancellation device and an echo cancellation method thereof applied in a communication device are provided. The echo cancellation device includes an echo canceller and a combine circuit. The echo canceller obtains a plurality of delayed signals from a local signal of the communication device, and the delayed signals are divided into a plurality of delayed signal groups. The echo canceller selectively ignores at least one of the delayed signal groups, and the echo canceller generates an echo cancellation signal with the others of the delayed signal groups. The combine circuit is coupled to an interface circuit of the communication device to receive a received signal. The combine circuit cancels an echo component of the received signal with the echo cancellation signal to generate a cancelled signal.
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公开(公告)号：US20230163740A1
公开(公告)日：2023-05-25
申请号：US17531811
申请日：2021-11-22
CPC分类号： H03G3/3084 , H03F3/45 , H03M1/12 , H04B10/6933 , H03F2200/375 , H03F2203/45212
摘要： A method for removing offset in a receiver of an integrated circuit (IC) includes: determining digital codes of differential input voltages of an amplifier in a first receiving lane of the receiver; comparing the digital codes to a digital code corresponding to an optimum common mode voltage (VCM) of the receiver; according to the comparison, determining a bias code for adjusting both the differential input voltages to match the optimum VCM; and inputting the bias code to a bias circuit of the receiver. The first receiving lane of the receiver includes a plurality of amplifiers. The method steps are repeated for each amplifier of the plurality of amplifiers, and then repeated for all receiving lanes of the IC.
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5.发明授权公开(公告)号：US11381222B2
公开(公告)日：2022-07-05
申请号：US17178194
申请日：2021-02-17
发明人： Ling Chen , Andrew Chao , Xiao-Dong Fei
摘要： An apparatus for performing baseline wander correction (BLWC) with the aid of differential wander current sensing includes filters and a correction circuit. The filters are positioned in a front-end circuit of a receiver and coupled to a set of input terminals of the receiver, and filter a set of input signals on the set of input terminals to generate a set of differential signals on a set of secondary terminals, for further usage by the receiver. The correction circuit is positioned in the frontend circuit and electrically connected to the set of input terminals and the set of secondary terminals, and performs BLWC on the set of differential signals according to the set of input signals. In the correction circuit, amplifiers and resistors form a differential wander current sensor to sense differential wander current, and a set of current mirrors generate corresponding baseline wander compensation current to perform BLWC.
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公开(公告)号：US10855437B1
公开(公告)日：2020-12-01
申请号：US16583234
申请日：2019-09-25
发明人： Ling Chen , Andrew Chao , Xiao-Dong Fei , Wei Liu
摘要： The present invention provides a clock data recovery apparatus and an operation method thereof. The clock data recovery apparatus includes an equalizer, a phase detector, a charge pump, and an oscillation circuit. The equalizer is configured to equalize raw data to generate equalized data. The phase detector is coupled to the equalizer to receive the equalized data. The phase detector is configured to generate a detection result according to the equalized data. The phase detector performs pattern-filtering on the equalized data to filter out at least one pattern. The charge pump is coupled to the phase detector to receive the detection result. The charge pump is configured to generate a control signal according to the detection result. The oscillation circuit is coupled to the charge pump to receive the control signal. The oscillation circuit is configured to generate a clock signal according to the control signal.
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公开(公告)号：US10833674B2
公开(公告)日：2020-11-10
申请号：US16554652
申请日：2019-08-29
发明人： Feng Xu , Shu Dong Wu , Zhen Liang Zhang
IPC分类号： H03K17/687 , H03K19/20 , H03M1/12
摘要： A switch device including a switch circuit and switch controller. The switch circuit comprises first and second switches to selectively enable a path between an input terminal and an output terminal. The switch controller refers to a selection signal and a switch signal to respectively generate a first switch control signal at a first switch control signal output terminal and a second switch control signal at a second switch control signal output terminal. When the voltage level of an input signal at the input terminal is larger than a power voltage, the switch controller generates the first switch control signal and the second switch control signal capable of turning off the switch circuit. When the voltage level of the input signal is not larger than the power voltage, the switch controller generates the first switch control signal and the second switch control signal according to the switch signal.
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公开(公告)号：US10749508B1
公开(公告)日：2020-08-18
申请号：US16525686
申请日：2019-07-30
发明人： Vinod Kumar Jain
摘要： A signal converter, a duty-cycle corrector, and a differential clock generator are provided. The differential clock generator includes the signal converter and the duty-cycle corrector. The signal converter is capable of calibrating skew distortion, and the duty-cycle corrector is capable of calibrating duty-cycle distortion. With the signal converter and the duty-cycle corrector, the differential clock generator can be applied to communication devices operating at high frequency.
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公开(公告)号：US09971369B1
公开(公告)日：2018-05-15
申请号：US15496129
申请日：2017-04-25
发明人： Chi-Yang Chen , Wen-Chi Huang
IPC分类号： G05F1/46
CPC分类号： G05F1/468
摘要： A voltage regulator is connected with an input/output circuit. The voltage regulator includes a controlling circuit, a sink voltage generator and a source voltage generator. The controlling circuit generates a first reference voltage, a second reference voltage, a first power start control signal and a second power start control signal. The sink voltage generator receives the first reference voltage and the first power start control signal. The source voltage generator receives the second reference voltage and the second power start control signal. When the voltage regulator is in a normal working state, the controlling circuit inactivates the first power start control signal and the second power start control signal, the sink voltage generator generates a sink voltage according to the first reference voltage, and the source voltage generator generates a source voltage according to the second reference voltage.
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公开(公告)号：US09641159B1
公开(公告)日：2017-05-02
申请号：US15046451
申请日：2016-02-18
发明人： Chiang-Hsiang Liao , Sheng-Hua Chen
CPC分类号： H03K3/0375 , H03K3/0372 , H03K3/3562
摘要： A flip-flop circuit including a first logic circuit, a first master latch, a second master latch, and a slave latch is provided. The first logic circuit operates a logic operation on a selecting signal and a clock signal to generate a first control signal. The first master latch receives a data signal according to the first control signal and latches the data signal according to the selecting signal and the clock signal. The second master latch receives a scan data signal according to the selecting signal and the clock signal, wherein an output terminal of the second master latch is directly connected to an output terminal of the first master latch. The slave latch latches a signal on the output terminals of the first and second master latches for generating an output signal.
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