摘要:
A receiver apparatus can identify a plurality of patterns corresponding to scrambled synchronization bytes of a transport stream in a number of successive signal frames containing FEC code blocks, determine a pattern distribution into which most of the patterns identified in the successive signal frames map, and generate a synchronization signal locked to a distribution of the FEC code blocks associated with the pattern distribution. With this synchronization signal, FEC code blocks can be timely handled in a reliable manner through a FEC decoder, making the receiver apparatus more efficient and robust. In other embodiments, methods of handling FEC code blocks in a receiver apparatus are also described.
摘要:
A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window. The SAR controller decodes the outputs of the first and second coarse comparators and the fine comparator to obtain a converted output of the SAR ADC.
摘要:
A method for frame rate up conversion. The method is executed by a frame rate up-converter. The frame rate up-converter receives a plurality of consecutive input video frames and detects luminance information for a current frame. The frame rate up-converter generates a first output frame according to the luminance information for the current frame and a preceding frame before the current frame and generates a second output frame according to the luminance information for the current frame and a succeeding frame after the current frame, wherein the second output frame is outputted after the first output frame.
摘要:
A decoder and related method adaptively generate a clock window. A falling edge of a horizontal synchronization signal is detected, and the time difference between an actual frame code and a predefined frame code is determined. The beginning and the end of the clock window are then adaptively determined based on the falling edge and the time difference, such that symbol timing recovery through received clock run-in signals may be performed within the generated clock window.
摘要:
A backlight control system and method are disclosed. An overdrive device modifies a backlight duty signal according to a current-frame backlight duty signal and a previous-frame backlight duty signal. In one embodiment, the overdrive device is implemented with a lookup table that outputs the modified backlight duty signal. The backlight driven by the modified backlight duty signal then emits light to a display panel, thereby increasing a response time of the backlight.
摘要:
A depth map generating device. A first depth information extractor extracts a first depth information from a main two dimensional (2D) image according to a first algorithm and generates a first depth map corresponding to the main 2D image. A second depth information extractor extracts a second depth information from a sub 2D image according to a second algorithm and generates a second depth map corresponding to the sub 2D image. A mixer mixes the first depth map and the second depth map according to adjustable weighting factors to generate a mixed depth map. The mixed depth map is utilized for converting the main 2D image to a set of three dimensional (3D) images.
摘要:
A backlight controller, a display device using the same and a method for controlling a backlight module are provided. The backlight controller includes a temporal weighting module and a dimming controlling module. The temporal weighting module calculates a weight sum of a first backlight luminance provided in a current frame and a target backlight luminance to serve as an adjusted backlight luminance. The target backlight luminance is obtained according to an image content of the current frame. The dimming controlling module increases or decreases the adjusted backlight luminance by a step value according to the target backlight luminance and generates a second backlight luminance provided in a next frame. Therefore, a backlight luminance of the backlight module not only can be smoothly adjusted to the target backlight luminance at high speed for avoiding backlight flicker, but also can be adaptive to image content for saving electric power consumption.
摘要:
A video processing apparatus. A first scaling module receives original images according to an original pixel clock and performs adjustments on the original images according to a first scaling ratio to generate first scaled images. A frame buffer buffers the first scaled images. A controller controls the frame buffer to receive the first scaled images according to a first pixel clock and output the first scaled images according to a second pixel clock. A second scaling module receives the first scaled images and performs adjustments on the first scaled images according to a second scaling ratio to generate second scaled images. A length of a vertical blanking interval of the second scaled images is longer than a length of a vertical blanking interval of the original images.
摘要:
A receiver with capability of correcting error is disclosed. A soft slicer generates quantized data and associated soft data. A decoder with error recovery generates decoded quantized data and a soft sequence, and is capable of correcting one bit of the quantized data. A serial-to-parallel (S/P) converter with code corrector generates parallel data, and is capable of correcting two bits of de-scrambled data bits.
摘要:
A channel estimation method for use with a received signal by a receiver is disclosed. The received signal comprises multiple data bursts which are transmitted to the receiver via multiple path channels, with each of the data bursts having a plurality of preamble symbols which are decoded. The channel estimation method includes the following steps: firstly, at least one correlation pattern is generated according to the decoded preamble symbols. Then, a cross correlation of the correlation pattern with the received signal is performed to yield at least one correlation result of channel impulse response (CIR). Wherein, the symbol boundary of the received signal is decided according to the correlation result.