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    Control pulse generator for the cyclical fault-free generation of an accurate sequence of control pulses
    1.
    发明授权
    Control pulse generator for the cyclical fault-free generation of an accurate sequence of control pulses 失效
    控制脉冲发生器用于循环无故障地产生精确的控制脉冲序列

    公开(公告)号：US4099129A

    公开(公告)日：1978-07-04

    申请号：US746620

    申请日：1976-12-01

    申请人： Heinz-Juergen Lohmann ,  Gerd Kopperschmidt

    发明人： Heinz-Juergen Lohmann ,  Gerd Kopperschmidt

    IPC分类号： H03K3/64 ,  H03K5/15 ,  H03K5/19

    CPC分类号： H03K5/15053 ,  H03K5/15013

    摘要： A control pulse generator for the cyclical fault-free generation of an accurate sequence of control pulses utilizing a quartz pulse generator which is operatively connected to and adapted to initiate actuation of a plurality of serially connected to delay members over a control circuit which is operative, at the termination of a cycle of actuation of the serially connected delay members, to limit the initiation of a succeeding cycle by a pulse from the generator to a predetermined period of time following termination of the first cycle of operation and functioning as a self-holding circuit when the period duration of the quartz generator signals coincide with the running time of the serially connected delay members. Further means are provided for checking the duration of the limiting period to insure proper operation.

    摘要翻译： 一种控制脉冲发生器，用于利用石英脉冲发生器周期性无故障地产生控制脉冲的精确序列，所述石英脉冲发生器可操作地连接到并适于在可操作的控制电路上启动多个串联连接到延迟部件的致动， 在串行连接的延迟构件的致动周期的终止时，通过来自发电机的脉冲将下一个循环的启动限制在第一操作周期结束后的预定时间段，并且用作自持 当石英发生器信号的周期持续时间与串行连接的延迟构件的运行时间一致时，电路。 提供了进一步的手段来检查限制期的持续时间以确保正确的操作。

    Clock reproduction circuit and elements used in the same
    5.
    发明授权
    Clock reproduction circuit and elements used in the same 失效
    时钟再现电路和元件使用相同

    公开(公告)号：US5889828A

    公开(公告)日：1999-03-30

    申请号：US757982

    申请日：1996-11-27

    申请人： Takumi Miyashita ,  Nobuaki Tomesakai

    发明人： Takumi Miyashita ,  Nobuaki Tomesakai

    IPC分类号： H03K5/13 ,  H03K5/15 ,  H03L7/081 ,  H03L7/085 ,  H03L7/087 ,  H03L7/089 ,  H03L7/095 ,  H03L7/099 ,  H03L7/113 ,  H04L7/033 ,  H03D3/24

    CPC分类号： H03L7/099 ,  H03K5/133 ,  H03K5/15053 ,  H03L7/0812 ,  H03L7/085 ,  H03L7/087 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/0893 ,  H03L7/0896 ,  H03L7/113 ,  H04L7/033 ,  H03L7/095

    摘要： A clock reproduction circuit for reproducing a data clock from a data signal is disclosed. The clock reproduction circuit includes a voltage controlled oscillator, a phase detector, a frequency error detection circuit and a charge pump whose output is controlled by the outputs of the phase detector and the frequency error detection circuit. A VCO clock output from the voltage controlled oscillator is synchronized with the data clock by the feedback loop consisting of these elements. The frequency error detection circuit detects a frequency error between the VCO clock and the data clock by detecting changes in the phases of the VCO clock at the transition edges of the data signal. Analog and digital frequency error detection circuits are disclosed. Further, improved circuit elements in the clock reproduction circuit are disclosed.

    摘要翻译： 公开了一种用于从数据信号再现数据时钟的时钟再生电路。 时钟再现电路包括压控振荡器，相位检测器，频率误差检测电路和电荷泵，其输出由相位检测器和频率误差检测电路的输出控制。 由压控振荡器输出的VCO时钟由与这些元件组成的反馈回路与数据时钟同步。 频率误差检测电路通过检测数据信号的转换边缘处的VCO时钟的相位变化来检测VCO时钟与数据时钟之间的频率误差。 公开了模拟和数字频率误差检测电路。 此外，公开了时钟再现电路中的改进的电路元件。

    Clock reproduction circuit and elements used in the same
    6.
    发明授权
    Clock reproduction circuit and elements used in the same 失效
    时钟再现电路和元件使用相同

    公开(公告)号：US5610954A

    公开(公告)日：1997-03-11

    申请号：US401793

    申请日：1995-03-10

    申请人： Takumi Miyashita ,  Nobuaki Tomesakai

    发明人： Takumi Miyashita ,  Nobuaki Tomesakai

    IPC分类号： H03K5/13 ,  H03K5/15 ,  H03L7/081 ,  H03L7/085 ,  H03L7/087 ,  H03L7/089 ,  H03L7/095 ,  H03L7/099 ,  H03L7/113 ,  H04L7/033 ,  H03D3/24

    CPC分类号： H03L7/099 ,  H03K5/133 ,  H03K5/15053 ,  H03L7/0812 ,  H03L7/085 ,  H03L7/087 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/0893 ,  H03L7/0896 ,  H03L7/113 ,  H04L7/033 ,  H03L7/095

    摘要： A clock reproduction circuit produces a data clock from a data signal. The clock reproduction circuit includes a voltage controlled oscillator, a phase detector, a frequency error detection circuit and a charge pump whose output is controlled by the outputs of the phase detector and the frequency error detection circuit. A VCO clock output from the voltage controlled oscillator is synchronized with the data clock by the feedback loop consisting of these elements. The frequency error detection circuit detects a frequency error between the VCO clock and the data clock by detecting changes in the phases of the VCO clock at the transition edges of the data signal. Analog and digital frequency error detection circuits are used. Further, improved circuit elements in the clock reproduction circuit used.

    摘要翻译： 时钟再现电路从数据信号产生数据时钟。 时钟再现电路包括压控振荡器，相位检测器，频率误差检测电路和电荷泵，其输出由相位检测器和频率误差检测电路的输出控制。 由压控振荡器输出的VCO时钟由与这些元件组成的反馈回路与数据时钟同步。 频率误差检测电路通过检测数据信号的转换边缘处的VCO时钟的相位变化来检测VCO时钟与数据时钟之间的频率误差。 使用模拟和数字频率误差检测电路。 此外，使用时钟再生电路中的改进的电路元件。

    Line synchronized interrupt generator
    7.
    发明授权
    Line synchronized interrupt generator 失效
    线路同步中断发生器

    公开(公告)号：US4103335A

    公开(公告)日：1978-07-25

    申请号：US763744

    申请日：1977-01-28

    申请人： Joseph D. Vitali

    发明人： Joseph D. Vitali

    IPC分类号： G06F13/24 ,  H03K5/00 ,  H03K5/15

    CPC分类号： H03K5/00006 ,  G06F13/24 ,  H03K5/15053 ,  Y10T307/609

    摘要： An interrupt generator comprising an optical coupler and a number of cascaded bidirectional one shots. The input of the optical coupler is coupled to AC powerlines which provide power to a computer. The output of the optical coupler is an isolated square wave signal having the same frequency as the AC powerline. This output is used to trigger the input of the first one shot in a string of one shots. The first one shot has an output which triggers the inputs of a second one shot, which, in turn, triggers the inputs of the third, etc. The one-shot outputs provide a series of even multiples of the AC powerline frequency each synchronized with the powerline. A selected output of one of the one shots is passed through a buffer to the computer as an indication of the optimum time to sample data in a real time data acquisition system.