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公开(公告)号:US20240315149A1
公开(公告)日:2024-09-19
申请号:US18183200
申请日:2023-03-14
Applicant: International Business Machines Corporation
Inventor: Andrea Ruffino , Mridula Prathapan , Peter Mueller , John Francis Bulzacchelli , Sudipto Chakraborty , Thomas Morf
Abstract: The present disclosure relates to a cryogenic integrated circuit, the circuit being a Complementary metal-oxide-semiconductor (CMOS) or Bipolar CMOS (BiCMOS) stacked circuit. The circuit comprises: a substrate, and a resonator formed on the substrate. The resonator comprises a meandered inductor formed in a specific metal layer of the stack, wherein the specific metal layer, when cooled below a critical temperature, becomes superconducting.
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公开(公告)号:US12089511B2
公开(公告)日:2024-09-10
申请号:US18165479
申请日:2023-02-07
Applicant: International Business Machines Corporation
Inventor: Aaron Finck , John Blair , April Carniol , Oliver Dial , Muir Kumph
Abstract: Devices and/or computer-implemented methods to facilitate ZZ cancellation between qubits are provided. According to an embodiment, a device can comprise a coupler device that operates in a first oscillating mode and a second oscillating mode. The device can further comprise a first superconducting qubit coupled to the coupler device based on a first oscillating mode structure corresponding to the first oscillating mode and based on a second oscillating mode structure corresponding to the second oscillating mode. The device can further comprise a second superconducting qubit coupled to the coupler device based on the first oscillating mode structure and the second oscillating mode structure.
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公开(公告)号:US12069967B2
公开(公告)日:2024-08-20
申请号:US17863213
申请日:2022-07-12
Applicant: Microsoft Technology Licensing, LLC
Inventor: Christopher A. Cantaloube
CPC classification number: H10N60/815 , H01L24/08 , H01L24/80 , H10N60/0912 , H10N60/12 , H10N60/805 , H10N69/00 , H01L2224/08146 , H01L2224/80895 , H01L2224/80896
Abstract: An integrated circuit is provided that comprises a first substrate having a plurality of conductive contact pads spaced apart from one another on a surface of the first substrate, a dielectric layer overlying the first substrate and the plurality of conductive contact pads, and a second substrate overlying the dielectric layer. A plurality of superconducting contacts extend through the second substrate and the dielectric layer to the first substrate, wherein each superconducting contact of the plurality of superconducting contacts is aligned with and in contact with a respective conductive contact pad of the plurality of conductive contact pads.
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公开(公告)号:US20240249770A1
公开(公告)日:2024-07-25
申请号:US18587872
申请日:2024-02-26
Applicant: PsiQuantum Corp,
Inventor: Faraz Najafi
CPC classification number: G11C11/44 , H10N60/30 , H10N60/83 , H10N60/84 , H10N69/00 , H10N60/01 , H10N60/85
Abstract: An example memory cell includes a superconducting loop configured to receive a write current and form a persistent current that stores a data bit in the superconducting loop. The example memory cell further includes a superconducting wire coupled to the superconducting loop and configured to selectively read-out the data bit in the superconducting loop in response to a control signal. An example method of reading data from the memory cell includes receiving, at the superconducting loop, a write current to store a data bit in a superconducting loop, and forming a persistent current that circulates in the superconducting loop as a stored data bit. The example method further includes, in accordance with a control signal, transferring, via a superconducting wire of the memory cell that is coupled to the superconducting loop, at least a portion of the persistent current to an output of the memory cell.
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公开(公告)号:US20240212884A1
公开(公告)日:2024-06-27
申请号:US18557693
申请日:2022-04-29
Applicant: GEORGIA TECH RESEARCH CORPORATION
Inventor: Lukas GRABER , Alfonso J. CRUZ , Zhiyang JIN , Chunmeng XU , Amrita GHOSH
CPC classification number: H01B12/04 , H01B13/0036 , H10N69/00
Abstract: Disclosed herein are cryogenic wires and methods of making and use thereof. For example, disclosed herein are cryogenic wires comprising a conductor having a mass density of 5000 kg/m3 or less; and a cladding material disposed around the conductor, the cladding material comprising a ductile and malleable metal, wherein the conductor comprises lithium, beryllium, calcium, sodium, magnesium, titanium, or a combination thereof. In some examples, the conductor comprises lithium or an alloy thereof, beryllium or an alloy thereof, calcium or an alloy thereof, sodium or an alloy thereof, magnesium or an alloy thereof, titanium or an alloy thereof, or a combination thereof.
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公开(公告)号:US12022745B2
公开(公告)日:2024-06-25
申请号:US17321462
申请日:2021-05-16
Applicant: Microsoft Technology Licensing, LLC
Inventor: Quang Thanh Tran , Judith Cutaran Aarts , John S. Hickman , Thanh Cong Dinh
CPC classification number: H10N60/01 , G06N10/00 , H01L21/67034 , H10N69/00
Abstract: Techniques are described herein that are capable of progressively thermally drying a quantum circuit. An inert gas is progressively heated by a heater element to provide a heated inert gas. Heated ambient air and the heated inert gas combine in a heating channel, causing a combination of the heated ambient air and the heated inert gas to flow into a probe compartment to progressively thermally dry a quantum circuit therein. A flow rate of the inert gas is controlled to cause the combination to have a relative humidity less than or equal to a threshold. A temperature of the heater element may be controlled to be approximately equal to a progressively increasing target temperature within a tolerance of 3.0° C. Heating of the inert gas may be initiated based on detection of the inert gas, and the flow and heating of the inert gas may be automatically discontinued.
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公开(公告)号:US12015397B2
公开(公告)日:2024-06-18
申请号:US17820721
申请日:2022-08-18
Applicant: International Business Machines Corporation
Inventor: Timothy Phung
Abstract: One or more systems, devices, and/or methods of manufacture and/or use provided herein relate to a quantum computing process to achieve higher connectivity of qubits to more than nearest neighbors and/or to a plurality of nearest neighbors. A system can comprise a tunable first coupler coupled to a first qubit, a tunable second coupler coupled to a second qubit, and a junction coupling the first coupler and the second coupler being both parametrically drivable. The first coupler and the second coupler can comprise superconducting quantum interference devices or Josephson junctions. The junction can comprise a central hub or central node separately coupled to the first coupler and the second coupler. The first coupler and the second coupler can be configured to capacitively or inductively couple the first qubit and the second qubit to one another to perform a control-Z (CZ) gate or an iSWAP gate.
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公开(公告)号:US20240196760A1
公开(公告)日:2024-06-13
申请号:US18537534
申请日:2023-12-12
Applicant: University of Tennessee Research Foundation
Inventor: Shamiul Alam , Ahmedullah Aziz , Mazharul Islam
IPC: H10N60/35 , G01R33/035 , G11C11/44 , H03K19/195 , H10N69/00
CPC classification number: H10N60/35 , G01R33/0354 , G11C11/44 , H03K19/195 , H10N69/00 , G06N10/40
Abstract: A cryogenic superconductive electronic assembly employable as a cryogenic superconductive logic gate assembly for control processors, and employable as a cryogenic superconductive memory array for memory devices and systems, is provided. Applications of use include quantum computers and superconducting electronics, as well as spacecraft electronics, among other possibilities. In varying implementations, the cryogenic superconductive electronic assembly is furnished with one or more superconducting quantum interference devices (SQUIDs) that are incorporated with a ferroelectric (FE) material, and are furnished with one or more heater cryotron (hTron) devices.
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公开(公告)号:US12009789B2
公开(公告)日:2024-06-11
申请号:US17081271
申请日:2020-10-27
Applicant: IQM Finland Oy
Inventor: Juha Hassel , Pasi Lähteenmäki
CPC classification number: H03F19/00 , H03K3/38 , H01L25/0657 , H01L25/105 , H03F2200/447 , H10N69/00
Abstract: A cryogenic integrated circuit or integrated module includes a travelling wave parametric amplifier or a Josephson parametric amplifier. The cryogenic integrated circuit or integrated module also includes an oscillator, a signal input, a biasing input, and a signal output. The oscillator is connected to an input of the amplifier and is configured to produce an oscillating drive signal. The signal input couples input signals into the amplifier. The biasing input couples biasing signals into the oscillator. The signal output conveys output signals from the amplifier out of the cryogenic integrated circuit or integrated module.
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公开(公告)号:US11972794B2
公开(公告)日:2024-04-30
申请号:US17967778
申请日:2022-10-17
Applicant: PsiQuantum Corp.
Inventor: Faraz Najafi
CPC classification number: G11C11/44 , H10N60/30 , H10N60/83 , H10N60/84 , H10N69/00 , H10N60/01 , H10N60/85
Abstract: An electronic device includes a substrate and a layer of superconducting material disposed over the substrate. The layer of superconducting material includes a first wire and a loop that is (1) distinct and separate from the first wire and (ii) capacitively coupled to the first wire while the loop and the first wire are in a superconducting state.
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