公开(公告)号：US20040257896A1

公开(公告)日：2004-12-23

申请号：US10753371

申请日：2004-01-09

发明人： Seong-Ho Jeung

IPC分类号： G11C005/00

CPC分类号： G11C7/06 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14

摘要： A semiconductor memory device and method of reading data from the semiconductor memory device is described. The semiconductor memory device may generate a data read clock signal that changes from a first logic state to a second logic state, and may read out bit cell data from a plurality of bit lines based on the generated data read clock signal. A word line signal and a dummy word line signal may be activated from the first logic state to the second logic state based on incoming X-address signals and Y-address signals. An enable signal may be output based on the activated dummy word signal, and a sense amplifier may sense the read-out bit cell data and a reference signal based on the activated enable signal, and output a corresponding to the sensed read-out bit cell data.

摘要翻译： 描述半导体存储器件和从半导体存储器件读取数据的方法。 半导体存储器件可以生成从第一逻辑状态变为第二逻辑状态的数据读取时钟信号，并且可以基于所生成的数据读取时钟信号从多个位线读出位单元数据。 基于输入的X地址信号和Y地址信号，字线信号和伪字线信号可以从第一逻辑状态激活到第二逻辑状态。 可以基于激活的伪字信号输出使能信号，并且读出放大器可以基于激活的使能信号感测读出位单元数据和参考信号，并且输出对应于感测的读出位单元 数据。

公开(公告)号：US20040255758A1

公开(公告)日：2004-12-23

申请号：US10496635

申请日：2004-05-21

发明人： Frank Klefenz ,  Karlheinz Brandenburg

IPC分类号： G11C005/00 ,  G10H007/00

CPC分类号： G10H1/00 ,  G10H2210/056 ,  G10H2240/145

摘要： In a method for generating an identifier for an audio signal including a tone generated by an instrument, a discrete amplitude-time representation of the audio signal is generated at first, wherein the amplitude-time representation, for a plurality of subsequent points in time, comprises a plurality of subsequent amplitude values, wherein a point in time is associated to each amplitude value. Subsequently, an identifier for the audio signal is extracted from the amplitude-time representation. An instrument database is formed from several identifiers for several audio signals including tones of several instruments. By means of a test identifier for an audio signal having been produced by an unknown instrument, the type of the test instrument is determined using the instrument database. A precise instrument identification can be obtained by using the amplitude-time representation of a tone produced by an instrument for identifying a musical instrument.

摘要翻译： 在用于产生包括由乐器产生的乐音的音频信号的标识符的方法中，首先产生音频信号的离散幅度 - 时间表示，其中对于多个随后的时间点的幅度 - 时间表示， 包括多个随后的幅度值，其中时间点与每个振幅值相关联。 随后，从振幅 - 时间表示中提取音频信号的标识符。 仪器数据库由若干音频信号的几个标识符形成，包括若干乐器的音调。 通过由未知仪器产生的音频信号的测试标识符，使用仪器数据库确定测试仪器的类型。 可以通过使用用于识别乐器的乐器产生的音调的振幅 - 时间表示来获得精确的乐器识别。

公开(公告)号：US20040252556A1

公开(公告)日：2004-12-16

申请号：US10856035

申请日：2004-05-28

发明人： Thomas M. Taylor ,  David Goslin

IPC分类号： G11C005/00 ,  A47K003/00 ,  A47K003/10

CPC分类号： E03B7/006 ,  E03B9/00 ,  G01N1/10

摘要： A water flushing system for a pressurized subterranean water distribution system includes an inlet conduit for receiving pressurized water from the subterranean water distribution system; an outlet fluidly connected to the inlet conduit for discharging pressurized water in the inlet conduit downwardly towards a drain; and a control valve for controlling the flow of pressurized water in the inlet conduit. The water flushing system further includes one or more of the following features: a freeze protection assembly, a detachable coupling system, a dechlorination system, and a backflow prevention system.

摘要翻译： 用于加压地下水分配系统的水冲洗系统包括用于从地下水分配系统接收加压水的入口管道; 流体连接到入口管道的出口，用于将入口管道中的加压水向下排放到排水口; 以及用于控制入口管道中的加压水流的控制阀。 水冲洗系统还包括以下特征中的一个或多个：防冻组件，可拆卸联接系统，脱氯系统和防回流系统。

公开(公告)号：US20040243872A1

公开(公告)日：2004-12-02

申请号：US10709765

申请日：2004-05-27

发明人： Li-Chun Tu ,  Hung-Cheng Kuo ,  Ping-Sheng Chen

IPC分类号： G11C005/00 ,  G06F012/00

CPC分类号： G06F9/3802 ,  G06F9/3814

摘要： A method for dynamically adjusting an operating speed of a microprocessor for the microprocessor to access at least a serial flash memory(together with a random access memory). The method includes reducing an executing speed of the microprocessor if the required data in the serial flash memory (or the random access memory) is not well prepared and executing the microprocessor at a normal speed if the required data in the serial flash memory(or the random access memory) is well prepared.

摘要翻译： 一种用于动态调整微处理器的操作速度以便微处理器访问至少串行闪存（与随机存取存储器）一起的方法。 如果串行闪存（或随机存取存储器）中所需的数据没有准备好并以正常速度执行微处理器（如果串行闪存中的所需数据（或 随机存取存储器）做好准备。

公开(公告)号：US20040240307A1

公开(公告)日：2004-12-02

申请号：US10803948

申请日：2004-03-19

申请人： SEIKO EPSON CORPORATION

发明人： Makoto Kudo

IPC分类号： G11C005/00

CPC分类号： G11C7/222 ,  G11C7/10 ,  G11C7/22

摘要： The invention can provide a device, such as a semiconductor device, that accesses at least one semiconductor storage medium. The semiconductor device can include a given bus master that functions as a bus master, a bus interface that controls access to semiconductor storage media based on access request from the bus master, and a clock-supply-control circuit that controls the presence of the supply of a clock to the bus master based on access state information that indicates a state of access to the semiconductor storage media. The clock-supply-control circuit can stop the supply of the clock to the bus master if the bus interface is at a BUSY state, and supply the clock to the bus master if the bus interface is not at a BUSY state. Accordingly, a power consumption of a semiconductor device that accesses at least one semiconductor storage medium can be reduced.

摘要翻译： 本发明可以提供访问至少一个半导体存储介质的诸如半导体器件的器件。 半导体器件可以包括用作总线主机的给定总线主机，基于来自总线主机的访问请求来控制对半导体存储介质的访问的总线接口，以及控制电源的存在的时钟供应控制电路 基于指示对半导体存储介质的访问状态的访问状态信息，向总线主机发送时钟。 如果总线接口处于BUSY状态，则时钟电源控制电路可以停止向总线主机供电时钟，如果总线接口不在BUSY状态，则将时钟提供给总线主机。 因此，可以减少访问至少一个半导体存储介质的半导体器件的功耗。

公开(公告)号：US20040240274A1

公开(公告)日：2004-12-02

申请号：US10749892

申请日：2003-12-31

发明人： Kie-Bong Ku

IPC分类号： G11C005/00

CPC分类号： G11C7/1069 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096

摘要： A semiconductor memory device including a main amplifier for amplifying an output from a bit line sensing amplifier and outputting the amplified output to a first data line; an input/output multiplexer connected to the first data line; a repeater connected to the first data line; an input/output write unit for receiving a data to be written and outputting the data to a second data line; and a write driver connected to the second data line for transferring the data on the second data line to the bit line sensing amplifier.

摘要翻译： 一种半导体存储器件，包括：主放大器，用于放大来自位线检测放大器的输出，并将放大的输出输出到第一数据线; 连接到第一数据线的输入/输出多路复用器; 连接到第一数据线的中继器; 输入/输出写入单元，用于接收要写入的数据并将数据输出到第二数据线; 以及连接到第二数据线的写驱动器，用于将第二数据线上的数据传送到位线感测放大器。

公开(公告)号：US20040233774A1

公开(公告)日：2004-11-25

申请号：US10847304

申请日：2004-05-18

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C005/00

CPC分类号： G11C16/08 ,  G11C11/22 ,  G11C16/0475 ,  H01L21/28282 ,  H01L21/28291 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/6684 ,  H01L29/7887

摘要： A semiconductor memory device includes a first nonvolatile memory cell, a bit line connected to the first nonvolatile memory cell, and a control circuit connected to the first nonvolatile memory cell and the bit line, and disposed and configured in such a manner as to reset the bit line to a predetermined first potential state only for a certain period nullanull of time in response to transition of an input address signal. The first nonvolatile memory cell has a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed under the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

摘要翻译： 半导体存储器件包括第一非易失性存储器单元，连接到第一非易失性存储器单元的位线和连接到第一非易失性存储单元和位线的控制电路，并且被配置和配置为使复位 位线到达预定的第一电位状态，仅响应于输入地址信号的转变而在一定时间段“a”。 第一非易失性存储单元具有通过栅极绝缘膜形成在半导体层上的栅电极; 设置在所述栅电极下方的沟道区域; 扩散区域设置在沟道区域的两侧并且具有与沟道区域的导电类型相反的导电类型; 以及形成在栅电极的两侧并具有保持电荷的功能的存储功能单元。

公开(公告)号：US20040233738A1

公开(公告)日：2004-11-25

申请号：US10879437

申请日：2004-06-29

发明人： Chris Cooper ,  Siang Tian Giam ,  Jerry D. McBride ,  Scott N. Gatzemeier ,  Scott L. Ayres ,  David R. Brown

IPC分类号： G11C005/00

CPC分类号： G11C29/006 ,  G01R31/31932 ,  G11C11/401 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/26 ,  G11C29/40 ,  G11C29/48 ,  G11C29/56 ,  G11C2029/5602

摘要： An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

摘要翻译： 公开了一种用于减小在芯片在半导体晶片上测试计算机存储器件，特别是Rambus DRAM所需的引脚驱动器计数的装置和方法。 通过减少引脚数量，可以同时测试更多的DRAM，从而降低测试成本和时间。 一个优选实施例利用预充电时钟的后沿选择新的活动存储体地址，使得选择新的活动地址所需的地址线不必与行线同时被访问。

公开(公告)号：US20040233733A1

公开(公告)日：2004-11-25

申请号：US10440855

申请日：2003-05-19

申请人： EMULEX CORPORATION

发明人： Eric Peel ,  Qing Xue ,  Sam Su ,  Stephen Eugene Holness

IPC分类号： G11C005/00

CPC分类号： G11C7/1006 ,  G11C7/22

摘要： The present invention is directed to a memory data interface for transferring data between a memory device and an integrated circuit, whereby, in accordance with one aspect of the present invention, the memory data interface includes a data selector for selecting and normalizing data from memory devices operating at different data transfer timing, and, in accordance with another aspect of the present invention, the memory data interface is capable of transferring data between a memory device and an integrated circuit having a different bus width than the memory device. In accordance with yet another aspect of the present invention, the memory data interface is capable of transferring data between an integrated circuit and a variety of different memory device having different data bus widths. Finally, in accordance with yet another aspect of the present invention, the memory data interface is capable of transferring data between an integrated circuit and a variety of memory devices having different bus widths and different data transfer timing.

摘要翻译： 本发明涉及一种用于在存储器件和集成电路之间传送数据的存储器数据接口，由此根据本发明的一个方面，存储器数据接口包括用于从存储器件中选择和归一化数据的数据选择器 在不同的数据传输定时操作，并且根据本发明的另一方面，存储器数据接口能够在存储器件和具有与存储器件不同的总线宽度的集成电路之间传送数据。 根据本发明的另一方面，存储器数据接口能够在集成电路和具有不同数据总线宽度的各种不同的存储器件之间传送数据。 最后，根据本发明的另一方面，存储器数据接口能够在集成电路和具有不同总线宽度和不同数据传输时序的各种存储器件之间传送数据。

公开(公告)号：US20040230736A1

公开(公告)日：2004-11-18

申请号：US10760631

申请日：2004-01-20

申请人： STMicroelectronics S.A.

发明人： Bruno Leconte ,  Sebastien Zink ,  Paola Cavaleri

IPC分类号： G11C005/00

CPC分类号： G11C16/08 ,  G11C8/08

摘要： An address decoder selectively applies to word lines of a memory array individual signals of variable polarity, negative or positive, the value of which varies according to a word line address applied to the decoder. The decoder comprises a group decoder delivering signals for selecting a group of word lines of variable polarity, at least one subgroup decoder delivering signals for selecting a subgroup of word lines of variable polarity, and word line drivers each comprising means for multiplexing the group and subgroup selection signals, for selecting and selectively applying one of these signals to a word line. Advantages: reduction in the size of the terminating elements of the decoders in relation with the reduction of the technological pitch in Flash memories.

摘要翻译： 地址解码器有选择地应用于存储器阵列的字线，根据应用于解码器的字线地址而变化的可变极性，负或正的各个信号。 解码器包括传送用于选择可变极性字线组的信号的组解码器，传送用于选择可变极性字线子组的信号的至少一个子组解码器，以及字线驱动器，每个字线驱动器包括用于复用组和子组 选择信号，用于选择并选择性地将这些信号中的一个施加到字线。 优点：减少解码器的端接元件的尺寸与减少闪存中技术间距有关。