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    Flame detecting system
    1.
    发明授权
    Flame detecting system 有权

    公开(公告)号：US09625311B2

    公开(公告)日：2017-04-18

    申请号：US15164248

    申请日：2016-05-25

    Applicant: Azbil Corporation

    Inventor： Raita Mori

    IPC: G01J1/42 ,  H01J19/82

    CPC classification number: G01J1/429 ,  G01J1/4204 ,  G01J5/0018 ,  G01J2001/444 ,  G01J2005/068 ,  H01J19/82

    Abstract: To easily obtain a quantity of received light with computation by only measuring pulses of an electric signal related to a flame sensor, a flame detecting system is disclosed comprising: a flame sensor to detect light and a calculating device, in which the calculating device includes an applied voltage generating portion configured to generate a pulse to drive the flame sensor, a voltage detecting portion configured to measure an electric signal flowing in the flame sensor, a storing portion configured to store sensitivity parameters of the flame sensor in advance, and a central processing unit configured to obtain a quantity of received light of a flame using parameters of a known quantity of received light, a pulse width, and a discharge probability of the sensitivity parameters, and a discharge probability obtained from an actual pulse width and the measured number of discharge times.

    Method and apparatus for detecting sudden temperature/voltage changes in integrated circuits
    2.
    发明授权
    Method and apparatus for detecting sudden temperature/voltage changes in integrated circuits 有权
    用于检测集成电路中突然的温度/电压变化的方法和装置

    公开(公告)号：US07831873B1

    公开(公告)日：2010-11-09

    申请号：US11715510

    申请日：2007-03-07

    Applicant: Stephen M. Trimberger ,  Austin H. Lesea

    Inventor： Stephen M. Trimberger ,  Austin H. Lesea

    IPC: G01R31/28 ,  G01R31/26 ,  H01L35/00 ,  H01L29/06 ,  H01J19/82 ,  G01K7/00

    CPC classification number: G01K3/005 ,  G01K7/32

    Abstract: An integrated circuit is used to monitor and process parametric variations, such as temperature and voltage variations. An integrated circuit may include a temperature-sensitive oscillator circuit and a temperature-insensitive oscillator circuit, and frequency difference between the two sources may be monitored. In some embodiments, a parametric-insensitive reference oscillator is used as a reference to measure frequency performance of a second oscillator wherein the second oscillator performance is parametric-sensitive. The measured frequency performance is then compared to a tamper threshold and the result of the comparison is indicative of tampering.

    Abstract translation: 集成电路用于监测和处理参数变化，如温度和电压变化。 集成电路可以包括温度敏感振荡器电路和不敏感温度的振荡器电路，并且可以监视两个源之间的频率差。 在一些实施例中，使用参数不敏感参考振荡器作为参考，以测量第二振荡器的频率性能，其中第二振荡器性能是参数敏感的。 然后将测量的频率性能与篡改阈值进行比较，并且比较的结果表示篡改。

    High speed mis-type intergrated circuit with self-regulated back bias
    3.
    发明授权
    High speed mis-type intergrated circuit with self-regulated back bias 失效
    具有自调节背偏的高速误差集成电路

    公开(公告)号：US5672995A

    公开(公告)日：1997-09-30

    申请号：US340343

    申请日：1994-11-14

    Applicant: Junji Hirase ,  Hironori Akamatsu ,  Susumu Akamatsu ,  Takashi Hori

    Inventor： Junji Hirase ,  Hironori Akamatsu ,  Susumu Akamatsu ,  Takashi Hori

    IPC: H01L27/04 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/10 ,  H01L27/108 ,  H01J19/82 ,  G05F1/10

    CPC classification number: H01L27/0218

    Abstract: There are provided a MIS transistor having a substrate portion, a gate, a source, and a drain, a back-bias generator to be applied to the substrate portion of the MIS transistor, and a resistor interposed between the substrate portion of the MIS transistor and the back-bias generator so that the potential between the both ends thereof changes in a range from one value in the active mode to the other value in the standby mode of the MIS transistor. In the MIS transistor, the back bias is self-regulated so that it approaches to zero in the active mode, while it moves away from zero in the standby mode. Consequently, the threshold voltage is reduced in the active mode due to the back bias approaching to zero, so that higher-speed operation is performed. On the other hand, off-state leakage is suppressed in the standby mode due to the back bias moving away from zero. Thus, it becomes possible to constitute a semiconductor apparatus which operates at high speed with low power consumption.

    Abstract translation: 提供了具有衬底部分，栅极，源极和漏极的MIS晶体管，施加到MIS晶体管的衬底部分的反向偏置发生器，以及插入在MIS晶体管的衬底部分之间的电阻器 和偏压发生器，使得其两端之间的电位在从动模式中的一个值到MIS晶体管的待机模式中的另一个值的范围内变化。 在MIS晶体管中，背偏压是自调节的，使得它在有功模式下接近零，而在待机模式下它偏离零。 因此，由于反向偏压接近零，所以在激活模式中阈值电压降低，从而执行更高速度的操作。 另一方面，由于背偏压偏离零，在待机模式下，截止状态泄漏被抑制。 因此，可以构成以低功耗高速运转的半导体装置。

    Redundant logic circuit
    4.
    发明授权
    Redundant logic circuit 失效
    冗余逻辑电路

    公开(公告)号：US3800164A

    公开(公告)日：1974-03-26

    申请号：US79051169

    申请日：1969-01-02

    Applicant: US NAVY

    Inventor： MILLER F

    IPC: H03K19/003 ,  H04B1/74 ,  H01J19/82 ,  G06F11/08

    CPC classification number: H03K19/00392 ,  H04B1/74

    Abstract: This invention is directed to a redundant logic system having a plurality of input channels and a single output channel. The system initially senses and compares the absolute magnitude of two of the input channels. When the magnitudes are identical, a switch is initiated in one of these channels to connect it to the output channel. When one of the channels fails, the compared output of the absolute magnitude detectors is utilized to insure that the channel which has failed is disconnected and that the operating channel is connected to the output channel. The failoperational capacity may be increased in a cascade fashion by utilizing the single output of the first channel together with another input channel. Monitoring means are also provided to detect where failures have occurred.

    Abstract translation: 本发明涉及具有多个输入通道和单个输出通道的冗余逻辑系统。 系统最初感测并比较了两个输入通道的绝对幅度。 当幅度相同时，在这些通道之一中启动开关以将其连接到输出通道。 当其中一个通道出现故障时，绝对幅度检测器的比较输出被用于确保故障通道断开，并且工作通道连接到输出通道。 可以通过利用第一通道的单个输出和另一个输入通道以级联方式增加故障操作容量。 还提供监控装置来检测发生故障的位置。

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