公开(公告)号：US07240320B1

公开(公告)日：2007-07-03

申请号：US10989679

申请日：2004-11-16

申请人： Stephen M. Trimberger ,  Austin H. Lesea ,  Bernard J. New

发明人： Stephen M. Trimberger ,  Austin H. Lesea ,  Bernard J. New

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A method of implementing a design on a programmable logic device (PLD) includes generating a database that identifies correspondence between resources and programming frames of the PLD. A first PLD design is compiled, wherein the first design uses a first set of resources in a first manner. Costs associated with using the first set of resources of the first design in the first manner are reduced. A second PLD design is then compiled, applying the reduced costs associated with using the first set of resources. A second set of resources required to compile the second design is identified, wherein the second set of resources is not used in the same manner as the first set of resources. A set of programming frames associated with the second set of resources is identified. Costs associated with using a third set of resources associated with the set of programming frames are increased.

摘要翻译： 在可编程逻辑器件（PLD）上实现设计的方法包括生成识别PLD的资源和编程帧之间的对应关系的数据库。 编译第一PLD设计，其​​中第一设计以第一方式使用第一组资源。 降低了以第一种方式使用第一种设计的第一组资源相关联的成本。 然后编制第二PLD设计，应用与使用第一组资源相关联的降低的成本。 识别编译第二设计所需的第二组资源，其中第二组资源不以与第一组资源相同的方式使用。 识别与第二组资源相关联的一组编程帧。 与使用与该组编程帧相关联的第三组资源相关联的成本增加。

公开(公告)号：US06849951B1

公开(公告)日：2005-02-01

申请号：US10377863

申请日：2003-02-28

申请人： Stephen M. Trimberger ,  Austin H. Lesea

发明人： Stephen M. Trimberger ,  Austin H. Lesea

IPC分类号： H01L23/528 ,  H01L23/64 ,  H01L25/065 ,  H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/642 ,  H01L24/48 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/16152 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A die having a bypass capacitor is stacked on another die having an active circuit. The active circuit draws a spike of current, for example, during a switching period of a voltage on its output lead from one digital logic level to another digital logic level. The bypass capacitor provides a portion of the spike of current through a conductive plug that extends from a plate of the bypass capacitor to a power lead of the active circuit. The length of the conductive plug is reduced by extending the conductive plug from the bypass capacitor to the active circuit orthogonally to the planar orientation of the dice. Reducing the length of the conductive plug reduces the resistance and inductance of the conductive plug and, in turn, reduces the drop in voltage between the voltage on the bypass capacitor and the voltage on the power lead of the active circuit.

摘要翻译： 具有旁路电容器的管芯堆叠在具有有源电路的另一管芯上。 有源电路例如在其输出引线上的电压从一个数字逻辑电平到另一数字逻辑电平的开关周期期间画出电流尖峰。 旁路电容器通过从旁路电容器的板延伸到有源电路的电源线的导电插头提供电流尖峰的一部分。 通过将导电插塞从旁路电容器延伸到与裸片的平面取向正交的有源电路，导电插头的长度减小。 降低导电插头的长度会降低导电插头的电阻和电感，进而降低旁路电容器上的电压与有源电路的电源线上的电压之间的电压降。

公开(公告)号：US08516339B1

公开(公告)日：2013-08-20

申请号：US13078172

申请日：2011-04-01

申请人： Austin H. Lesea ,  Stephen M. Trimberger

发明人： Austin H. Lesea ,  Stephen M. Trimberger

IPC分类号： G11C29/00

CPC分类号： G11C29/42 ,  G06F11/1012 ,  G11C11/41 ,  G11C29/44 ,  G11C29/52 ,  H03M13/2906 ,  H03M13/2927 ,  H03M13/37

摘要： A method of correcting adjacent bit errors in a memory is disclosed. The method comprises determining that there are errors in each set of two non-overlapping sets of the memory; changing a stored value of a memory cell of the memory until it is determined that a single error exists in the memory; identifying a location of the single error in the memory; and correcting the single error in the memory. A circuit for detecting adjacent bit errors in a memory having alternating even memory cells and odd memory cells is also disclosed.

摘要翻译： 公开了一种校正存储器中相邻位错误的方法。 该方法包括确定存储器的两组非重叠集合的每组中存在错误; 改变存储器的存储单元的存储值，直到确定存储器中存在单个错误为止; 识别存储器中单个错误的位置; 并纠正存储器中的单个错误。 还公开了一种用于检测具有交替的均匀存储单元和奇数存储单元的存储器中的相邻位错误的电路。

公开(公告)号：US08386990B1

公开(公告)日：2013-02-26

申请号：US12961753

申请日：2010-12-07

申请人： Stephen M. Trimberger ,  Austin H. Lesea

发明人： Stephen M. Trimberger ,  Austin H. Lesea

IPC分类号： G06F17/50 ,  G06F19/00 ,  H01L23/58 ,  H01L25/00 ,  H03K19/00

CPC分类号： G06F21/73 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the invention relates to an integrated circuit such as an FPGA wherein a stable unique identifier is produced by reading an intrinsic characteristic of the IC such as a physically unclonable function, and a related method. In one embodiment, a first unique identifier is generated using the intrinsic characteristic and is subdivided into a plurality of first subsets. A second unique identifier is received and subdivided into a plurality of second subsets. The first and second subsets are compared to identify matching subsets to generate the stable unique identifier. Each of the one or more matching subsets includes a particular one of the plurality of first subsets that matches a corresponding one of the plurality of second subsets. The stable unique identifier can be integrated into logic of the IC. Prior to comparing the subsets, the first and second subsets can be transformed with one-way functions.

摘要翻译： 本发明的实施例涉及诸如FPGA的集成电路，其中通过读取诸如物理不可克隆功能的IC的固有特性来产生稳定的唯一标识符，以及相关方法。 在一个实施例中，使用本征特征生成第一唯一标识符，并将其细分为多个第一子集。 接收第二唯一标识符并将其细分成多个第二子集。 比较第一和第二子集以识别匹配子集以产生稳定的唯一标识符。 所述一个或多个匹配子集中的每一个包括与所述多个第二子集中的相应一个匹配的所述多个第一子集中的特定一个子集。 稳定的唯一标识符可以集成到IC的逻辑中。 在比较子集之前，第一和第二子集可以用单向函数进行变换。

公开(公告)号：US06525560B1

公开(公告)日：2003-02-25

申请号：US10017516

申请日：2001-12-12

申请人： Stephen M. Trimberger ,  Austin H. Lesea

发明人： Stephen M. Trimberger ,  Austin H. Lesea

IPC分类号： H03K19173

CPC分类号： H03K19/17748

摘要： A programmable logic device (PLD) includes a die having first and second bond pads, each being weakly pulled to a first voltage. A package enclosing the die has an external pad configured to receive a second voltage. A conductor couples one and only one of the first and second bond pads to the external pad, such that one bond pad is pulled to the first voltage, and the other bond pad is pulled to the second voltage. A logic circuit on the die is coupled the first and second bond pads. The logic circuit enables the PLD to be configured in response to a first type of bit stream if the first bond pad is pulled to the second voltage, and enables the PLD to be configured only in response to a second type of bit stream if the second bond pad is pulled to the second voltage. In another embodiment, a bond pad is weakly pulled to a first voltage, and can be connected or not connected to an external pin for applying a second voltage.

摘要翻译： 可编程逻辑器件（PLD）包括具有第一和第二接合焊盘的管芯，每个引脚被弱拉至第一电压。 封装芯片的封装具有被配置为接收第二电压的外部焊盘。 导体将第一和第二接合焊盘中的一个并且仅一个耦合到外部焊盘，使得一个焊盘被拉到第一电压，而另一个焊盘被拉到第二电压。 芯片上的逻辑电路耦合第一和第二接合焊盘。 如果第一接合焊盘被拉到第二电压，则逻辑电路使得能够响应于第一类型的位流来配置PLD，并且使得仅当响应于第二类型的位流而配置PLD时 接合焊盘被拉到第二电压。 在另一个实施例中，接合焊盘被弱拉至第一电压，并且可以连接或不连接到用于施加第二电压的外部引脚。

公开(公告)号：US09213835B2

公开(公告)日：2015-12-15

申请号：US12755792

申请日：2010-04-07

申请人： Austin H. Lesea ,  Stephen M. Trimberger

发明人： Austin H. Lesea ,  Stephen M. Trimberger

IPC分类号： G06F21/00 ,  G06F21/55 ,  G06F21/72

CPC分类号： G06F21/72 ,  G06F21/755

摘要： In one embodiment of the present invention, a secure cryptographic circuit arrangement is provided. The secure cryptographic circuit includes a cryptographic processing block, a spreading sequence generator, and a delay control circuit. The cryptographic processing block has a plurality of signal paths. One or more of the plurality of signal paths includes respective adjustable delay circuits. The spreading sequence generator is configured to output a sequence of pseudo-random numbers. The delay control circuit has an input coupled to an output of the spreading sequence number generator and one or more outputs coupled to respective delay adjustment inputs of the adjustable delay circuits. The delay control circuit is configured to adjust the adjustable delay circuits based on the pseudo-random numbers.

摘要翻译： 在本发明的一个实施例中，提供了一种安全密码电路装置。 安全密码电路包括密码处理块，扩展序列发生器和延迟控制电路。 密码处理块具有多个信号路径。 多个信号路径中的一个或多个包括相应的可调延迟电路。 扩展序列生成器被配置为输出伪随机数序列。 延迟控制电路具有耦合到扩展序列号发生器的输出的输入和耦合到可调节延迟电路的相应延迟调整输入的一个或多个输出。 延迟控制电路被配置为基于伪随机数来调整可调延迟电路。

公开(公告)号：US08155907B1

公开(公告)日：2012-04-10

申请号：US12480488

申请日：2009-06-08

申请人： Austin H. Lesea ,  Stephen M. Trimberger ,  Christopher H. Kingsley ,  Satyaki Das ,  Tim Tuan

发明人： Austin H. Lesea ,  Stephen M. Trimberger ,  Christopher H. Kingsley ,  Satyaki Das ,  Tim Tuan

IPC分类号： G06F11/00 ,  G06F19/00 ,  G06F17/40

CPC分类号： G06F17/5045 ,  G06F11/26 ,  G06F2217/86

摘要： Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice have a common layout of the different element types for implementing the circuits; receiving output data from the plurality of dice in response to applying the test data to the plurality of dice; analyzing the output data from the plurality of dice; transforming by a computer the output data to characterization data comprising timing data associated with the different element types for implementing circuits, wherein the characterization data comprises data associated with regions of the dice, and storing the characterization data. A computer program product for enabling functions of a design to be implemented in an integrated circuit device is also disclosed.

摘要翻译： 公开了在集成电路装置中实现设计功能的方法。 示例性方法包括将测试数据应用于具有用于实现电路的不同元件类型的多个骰子，其中所述多个骰子具有用于实现电路的不同元件类型的公共布局; 响应于将所述测试数据应用于所述多个骰子，从所述多个骰子接收输出数据; 分析来自多个骰子的输出数据; 通过计算机将输出数据转换成包括与用于实现电路的不同元件类型相关联的定时数据的表征数据，其中表征数据包括与骰子区域相关联的数据，并存储表征数据。 还公开了一种用于使得能够在集成电路器件中实现设计功能的计算机程序产品。

公开(公告)号：US20110252244A1

公开(公告)日：2011-10-13

申请号：US12755792

申请日：2010-04-07

申请人： Austin H. Lesea ,  Stephen M. Trimberger

发明人： Austin H. Lesea ,  Stephen M. Trimberger

IPC分类号： H04L9/06 ,  G06F21/00

CPC分类号： G06F21/72 ,  G06F21/755

摘要： In one embodiment of the present invention, a secure cryptographic circuit arrangement is provided. The secure cryptographic circuit includes a cryptographic processing block, a spreading sequence generator, and a delay control circuit. The cryptographic processing block has a plurality of signal paths. One or more of the plurality of signal paths includes respective adjustable delay circuits. The spreading sequence generator is configured to output a sequence of pseudo-random numbers. The delay control circuit has an input coupled to an output of the spreading sequence number generator and one or more outputs coupled to respective delay adjustment inputs of the adjustable delay circuits. The delay control circuit is configured to adjust the adjustable delay circuits based on the pseudo-random numbers.

摘要翻译： 在本发明的一个实施例中，提供了一种安全密码电路装置。 安全密码电路包括密码处理块，扩展序列发生器和延迟控制电路。 密码处理块具有多个信号路径。 多个信号路径中的一个或多个包括相应的可调延迟电路。 扩展序列生成器被配置为输出伪随机数序列。 延迟控制电路具有耦合到扩展序列号发生器的输出的输入和耦合到可调节延迟电路的相应延迟调整输入的一个或多个输出。 延迟控制电路被配置为基于伪随机数来调整可调延迟电路。

公开(公告)号：US07979827B1

公开(公告)日：2011-07-12

申请号：US12042527

申请日：2008-03-05

申请人： Stephen M. Trimberger ,  Austin H. Lesea

发明人： Stephen M. Trimberger ,  Austin H. Lesea

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A method of configuring a device having programmable logic is disclosed. The method comprises generating a netlist associated with a circuit design; coupling the netlist to the device having programmable logic; performing a re-targeting function using a circuit on the device having programmable logic; generating configuration bits for configuring the programmable logic; and configuring the programmable logic to implement the circuit design according to the configuration bits based upon the netlist and results of the re-targeting function.

摘要翻译： 公开了一种配置具有可编程逻辑的装置的方法。 该方法包括生成与电路设计相关联的网表; 将网表耦合到具有可编程逻辑的设备; 使用具有可编程逻辑的设备上的电路执行重定向功能; 生成用于配置可编程逻辑的配置位; 以及根据重定向功能的网表和结果，根据配置位配置可编程逻辑以实现电路设计。

公开(公告)号：US07268581B1

公开(公告)日：2007-09-11

申请号：US11111229

申请日：2005-04-21

申请人： Stephen M. Trimberger ,  Austin H. Lesea

发明人： Stephen M. Trimberger ,  Austin H. Lesea

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K19/17736

摘要： A programmable logic device (PLD) includes a plurality of configurable resources, a programmable interconnect having a plurality of signal lines for providing a number of dedicated signal paths between any of the configurable resources, and a subway routing system having a shared subway bus coupled to the signal lines of the programmable interconnect at a plurality of connection points by a plurality of corresponding subway ports. The subway routing system, which provides alternate routing resources for the programmable interconnect, may be used to route different signals between different configurable resources at different times.

摘要翻译： 可编程逻辑器件（PLD）包括多个可配置资源，可编程互连具有多个信号线，用于在任何可配置资源之间提供多个专用信号路径，以及具有共享地铁总线的地铁路由系统， 由多个相应的地铁端口在多个连接点处的可编程互连的信号线。 为可编程互连提供备用路由资源的地铁路由系统可用于在不同时间在不同的可配置资源之间路由不同的信号。