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    High speed mis-type intergrated circuit with self-regulated back bias
    1.
    发明授权
    High speed mis-type intergrated circuit with self-regulated back bias 失效
    具有自调节背偏的高速误差集成电路

    公开(公告)号：US5672995A

    公开(公告)日：1997-09-30

    申请号：US340343

    申请日：1994-11-14

    申请人： Junji Hirase ,  Hironori Akamatsu ,  Susumu Akamatsu ,  Takashi Hori

    发明人： Junji Hirase ,  Hironori Akamatsu ,  Susumu Akamatsu ,  Takashi Hori

    IPC分类号： H01L27/04 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/10 ,  H01L27/108 ,  H01J19/82 ,  G05F1/10

    CPC分类号： H01L27/0218

    摘要： There are provided a MIS transistor having a substrate portion, a gate, a source, and a drain, a back-bias generator to be applied to the substrate portion of the MIS transistor, and a resistor interposed between the substrate portion of the MIS transistor and the back-bias generator so that the potential between the both ends thereof changes in a range from one value in the active mode to the other value in the standby mode of the MIS transistor. In the MIS transistor, the back bias is self-regulated so that it approaches to zero in the active mode, while it moves away from zero in the standby mode. Consequently, the threshold voltage is reduced in the active mode due to the back bias approaching to zero, so that higher-speed operation is performed. On the other hand, off-state leakage is suppressed in the standby mode due to the back bias moving away from zero. Thus, it becomes possible to constitute a semiconductor apparatus which operates at high speed with low power consumption.

    摘要翻译： 提供了具有衬底部分，栅极，源极和漏极的MIS晶体管，施加到MIS晶体管的衬底部分的反向偏置发生器，以及插入在MIS晶体管的衬底部分之间的电阻器 和偏压发生器，使得其两端之间的电位在从动模式中的一个值到MIS晶体管的待机模式中的另一个值的范围内变化。 在MIS晶体管中，背偏压是自调节的，使得它在有功模式下接近零，而在待机模式下它偏离零。 因此，由于反向偏压接近零，所以在激活模式中阈值电压降低，从而执行更高速度的操作。 另一方面，由于背偏压偏离零，在待机模式下，截止状态泄漏被抑制。 因此，可以构成以低功耗高速运转的半导体装置。

    Semiconductor integrated circuit including memory macro
    2.
    发明授权
    Semiconductor integrated circuit including memory macro 有权
    半导体集成电路包括内存宏

    公开(公告)号：US07451363B2

    公开(公告)日：2008-11-11

    申请号：US10300227

    申请日：2002-11-19

    申请人： Marefusa Kurumada ,  Hironori Akamatsu

    发明人： Marefusa Kurumada ,  Hironori Akamatsu

    IPC分类号： G11C29/00

    CPC分类号： G11C29/808 ,  G11C29/812

    摘要： The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macros includes a memory cell array connected to word lines and bit lines and a redundant circuit that replaces a defective bit line of the memory cell array to a normal bit line and a redundant bit line and outputs defect information to a redundant signal line. The redundant memory macro includes a redundant memory cell array connected to redundant word lines and the redundant bit line, and a first word line connection circuit that connects a word line corresponding to a memory macro to be repaired and disconnects a word line corresponding to a normal memory macro from the redundant word line.

    摘要翻译： 本发明提供了一种通过在多个SRAM宏中共享冗余存储器宏来提高区域效率和修复效率的半导体集成电路。 多个存储宏中的每一个包括连接到字线和位线的存储单元阵列和冗余电路，其将存储单元阵列的有缺陷位线替换为正常位线和冗余位线，并将缺陷信息输出到 冗余信号线。 冗余存储器宏包括连接到冗余字线和冗余位线的冗余存储单元阵列，以及第一字线连接电路，其连接对应于要修复的存储器宏的字线，并断开与正常对应的字线 来自冗余字线的存储器宏。

    Semiconductor memory device and circuit layout of dummy cell
    3.
    发明授权
    Semiconductor memory device and circuit layout of dummy cell 有权
    半导体存储器件和虚拟电池的电路布局

    公开(公告)号：US07136318B2

    公开(公告)日：2006-11-14

    申请号：US11156706

    申请日：2005-06-21

    申请人： Hirohisa Ohtsuki ,  Kazuo Itoh ,  Katsuji Satomi ,  Hironori Akamatsu

    发明人： Hirohisa Ohtsuki ,  Kazuo Itoh ,  Katsuji Satomi ,  Hironori Akamatsu

    IPC分类号： G11C7/02

    CPC分类号： G11C7/08 ,  G11C7/12 ,  G11C7/227 ,  G11C11/413

    摘要： A dummy cell includes two series-connected OFF-state transistors, one end of the series circuit which is formed by these two transistors is connected with a constant voltage source, and the other end of the series circuit is connected with a replica bit line. This suppresses a leak current flowing from the replica bit line to the dummy cell and therefore gives optimal start-up timing to a sense amplifier circuit.

    摘要翻译： 虚拟单元包括两个串联的截止状态晶体管，由这两个晶体管形成的串联电路的一端与恒定电压源连接，串联电路的另一端与复制位线连接。 这抑制了从复制位线流向虚拟单元的泄漏电流，从而给读出放大器电路提供了最佳的启动时序。

    Semiconductor integrated circuit with voltage-detecting circuit and signal transmitting and receiving system
    5.
    发明授权
    Semiconductor integrated circuit with voltage-detecting circuit and signal transmitting and receiving system 失效
    具有电压检测电路和信号发射和接收系统的半导体集成电路

    公开(公告)号：US06944003B2

    公开(公告)日：2005-09-13

    申请号：US10365527

    申请日：2003-02-13

    申请人： Hirokazu Sugimoto ,  Takashi Hirata ,  Hironori Akamatsu ,  Toru Iwata ,  Satoshi Takahashi

    发明人： Hirokazu Sugimoto ,  Takashi Hirata ,  Hironori Akamatsu ,  Toru Iwata ,  Satoshi Takahashi

    IPC分类号： G01R31/28 ,  H01L21/66 ,  H02H9/04 ,  H02H3/24

    CPC分类号： H02H9/046

    摘要： A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly. Consequently, even when the power supply voltage is made lower than the set voltage-detecting level, the first semiconductor integrated circuit properly operates until the power supply voltage reaches a predetermined lower limit of operating voltage. Thus, evaluation of operation is possible under low-voltage conditions.

    摘要翻译： 第一半导体集成电路通过电缆连接到第二半导体集成电路。 在第一半导体集成电路中，当电源电压变得小于设定电压检测电平时，电压检测电路输出电压检测信号来降低电缆的电压并停止工作。 第二半导体集成电路检测电缆的电压的降低以识别第一半导体集成电路的操作停止。 在这样配置的第一半导体集成电路中，在电源电压小于设定电压检测电平的低电压条件下进行测试时，电压检测电路从外部端子接收控制信号，停止动作 强制。 因此，即使电源电压低于设定电压检测电平，第一半导体集成电路也可以正常工作，直到电源电压达到预定的工作电压下限。 因此，在低电压条件下可以进行运行评估。

    Semiconductor integrated circuit and semiconductor integrated circuit system having serially interconnectable data buses
    6.
    发明授权
    Semiconductor integrated circuit and semiconductor integrated circuit system having serially interconnectable data buses 有权
    具有串行可互连数据总线的半导体集成电路和半导体集成电路系统

    公开(公告)号：US06297675B1

    公开(公告)日：2001-10-02

    申请号：US09478530

    申请日：2000-01-06

    申请人： Hironori Akamatsu ,  Yutaka Terada ,  Takashi Hirata ,  Yukio Arima ,  Satoshi Takahashi ,  Tadahiro Yoshida ,  Yoshihide Komatsu ,  Hiroyuki Yamauchi

    发明人： Hironori Akamatsu ,  Yutaka Terada ,  Takashi Hirata ,  Yukio Arima ,  Satoshi Takahashi ,  Tadahiro Yoshida ,  Yoshihide Komatsu ,  Hiroyuki Yamauchi

    IPC分类号： H03B100

    CPC分类号： H03K19/018514 ,  Y10T307/549

    摘要： A data line pair and a strobe line pair are provided between first and second chips to exchange data therebetween. The first chip includes an output circuit and a controller for controlling the output circuit. The second chip includes an input circuit. For example, the output circuit supplies a direct current from a power supply to one of the data lines. Then, the input circuit feeds back the received current to the output circuit through a pair of terminal resistors and the other data line. Subsequently, the output circuit supplies the fed back direct current to one of the strobe lines. In response, the input circuit feeds back the received current again to the output circuit through another pair of terminal resistors and the other strobe line. And then the fed back current is drained to the ground. Thus, compared to driving the data and strobe line pairs separately with the same amount of current supplied, the current dissipation can be halved. In this manner, the present invention is applicable to reduction of current dissipation when data should be transmitted at high speeds through multiple data bus pairs that are driven with a current supplied.

    摘要翻译： 在第一和第二芯片之间提供数据线对和选通线对，以在它们之间交换数据。 第一芯片包括输出电路和用于控制输出电路的控制器。 第二芯片包括输入电路。 例如，输出电路将电流从电源提供给数据线之一。 然后，输入电路通过一对端子电阻和另一条数据线将接收的电流反馈到输出电路。 随后，输出电路将反馈的直流电流提供给选通线之一。 作为响应，输入电路通过另一对端子电阻器和另一个选通线路将接收到的电流再次反馈到输出电路。 然后将反馈电流排到地面。 因此，与以相同的电流量驱动数据和选通线对相比，电流消耗可以减半。 以这种方式，本发明可应用于当通过以所提供的电流驱动的多个数据总线对以高速传输数据时，减少电流消耗。

    Semiconductor integrated circuit with multiple selectively activated synchronization circuits
    7.
    发明授权
    Semiconductor integrated circuit with multiple selectively activated synchronization circuits 失效
    具有多个选择性激活的同步电路的半导体集成电路

    公开(公告)号：US06236251B1

    公开(公告)日：2001-05-22

    申请号：US09261685

    申请日：1999-03-03

    申请人： Hironori Akamatsu

    发明人： Hironori Akamatsu

    IPC分类号： H03L700

    CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C7/1072 ,  G11C7/22 ,  H03L7/07 ,  H03L7/0812

    摘要： A semiconductor integrated circuit provided on a semiconductor chip includes a first synchronization circuit for receiving an external clock signal supplied from outside the semiconductor chip and outputting a first internal clock signal synchronized with the external clock signal and usable inside the semiconductor chip; a second synchronization circuit for receiving the first internal clock signal and outputting a second internal clock signal synchronized with the first internal clock signal and usable inside the semiconductor chip; and a functional block operable in synchronization with the second internal clock signal.

    摘要翻译： 设置在半导体芯片上的半导体集成电路包括：第一同步电路，用于接收从半导体芯片外部提供的外部时钟信号，并输出与外部时钟信号同步的第一内部时钟信号，并可在半导体芯片的内部使用; 第二同步电路，用于接收第一内部时钟信号并输出​​与第一内部时钟信号同步的第二内部时钟信号，并可在半导体芯片内使用; 以及与第二内部时钟信号同步操作的功能块。

    Static random access memory capable of reducing stendly power consumption and off-leakage current
    10.
    发明授权
    Static random access memory capable of reducing stendly power consumption and off-leakage current 失效
    静态随机存取存储器能够降低待机功耗和漏电流

    公开(公告)号：US5764566A

    公开(公告)日：1998-06-09

    申请号：US893682

    申请日：1997-07-11

    申请人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

    发明人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

    IPC分类号： G11C11/412 ,  G11C11/417 ,  G11C11/413

    CPC分类号： G11C11/412 ,  G11C11/417

    摘要： When a memory chip is in a standby mode, a ground power supply line of a flip-flop forming a memory cell is intermittently placed in the floating state. A switching NMOS transistor is connected between the ground power supply line and a power supply VSS. The gate of the NMOS transistor is controlled by an activation signal. When entering the floating state, the ground power supply line is charged due to an off-leakage current flowing in the transistor of the memory cell. As a result, the voltage of the ground power supply line is increased from the voltage of the power supply VSS. Accordingly, the off-leakage current of the memory cell is reduced, whereby the standby-time power consumption of the memory chip is decreased. When the voltage of the ground power supply line keeps going up, it becomes impossible to read data held in the memory cell in a short time, resulting in the data being lost. In order to prevent the loss of the data, the switching NMOS transistor is made to intermittently turn on.

    摘要翻译： 当存储器芯片处于待机模式时，形成存储单元的触发器的接地电源线被间歇地置于浮置状态。 开关NMOS晶体管连接在接地电源线和电源VSS之间。 NMOS晶体管的栅极由激活信号控制。 当进入浮动状态时，由于在存储单元的晶体管中流过的漏电流导致接地电源线被充电。 结果，接地电源线的电压从电源VSS的电压增加。 因此，存储单元的泄漏电流减小，从而存储芯片的待机时功耗降低。 当接地电源线的电压持续上升时，不可能在短时间内读取保存在存储单元中的数据，导致数据丢失。 为了防止数据丢失，使开关式NMOS晶体管间歇地导通。