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公开(公告)号：US5537498A
公开(公告)日：1996-07-16
申请号：US27049
申请日：1993-03-05
CPC分类号： H04L7/0075 , G02B6/43 , G06F1/105 , H04J3/0685
摘要： A clock distribution system minimizes clock skew in the distribution of clock signals to individual circuit board components in a highly synchronous, high speed computer system. The clock system includes an optical subsystem and an electrical subsystem. The optical subsystem utilizes multiple lasers and an n.times.n passive star coupler to introduce clock redundancy into the system. The lengths of the optical distribution fibers are controlled such that they are of equivalent optical path length. Once delivered to the logic assemblies, the optical clock signals are converted into equivalent electrical clock signals. The electrical subsystem then distributes the converted electrical clock signals to individual circuit board components over equalized fanout paths such that the skew as seen by the individual components is minimized. The system also compensates for skew introduced by the receiver and fanout electronics by tuning the length of the fiber. The electrical subsystem further includes means for customizing the fanout to fit individual circuit boards such that extraneous system noise is reduced. The overall clock system results in a maximum clock distribution network skew of approximately .+-.100 picoseconds, thus reducing or eliminating the need to perform electrical deskew at the individual circuit board components.
摘要翻译： 时钟分配系统将时钟信号的时钟偏差最小化到高度同步的高速计算机系统中的各个电路板组件。 时钟系统包括光学子系统和电子系统。 光学子系统利用多个激光器和nxn无源星形耦合器将时钟冗余引入系统。 控制光分配纤维的长度，使其具有等效的光程长度。 一旦传送到逻辑组件，光时钟信号被转换成等效的电时钟信号。 然后，电气子系统通过均衡的扇出路径将转换的电时钟信号分配给各个电路板部件，使得由各个部件所看到的偏斜最小化。 该系统还通过调整光纤的长度来补偿由接收器和扇出电子器件引入的偏斜。 电气子系统还包括用于定制扇出以适合各个电路板的装置，从而减少了外部系统噪声。 总体时钟系统导致大约+/- 100皮秒的最大时钟分配网络偏移，从而减少或消除在各个电路板组件处执行电消相校正的需要。
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92.发明授权Method and apparatus for locking shared memory locations in multiprocessing systems 失效用于锁定多处理系统中的共享存储器位置的方法和装置
公开(公告)号：US5535365A
公开(公告)日：1996-07-09
申请号：US141259
申请日：1993-10-22
摘要： A method of synchronizing accesses to shared data in a multiprocessing system having an atomic swap capability. A distinguished lock value is defined. A processor which wishes to access a shared data memory location performs an atomic swap of the lock value to the shared data memory location. If the data received from the atomic swap is equivalent to the lock value the processor knows that the memory location has been locked by another processor. The processor then repeats the atomic swap at intervals until data is received which is not equivalent to the lock value. The processor operates on the data and then performs a write to the shared data memory location to replace the lock value with the updated data. In an alternate embodiment, in situations where a unique lock value cannot be defined, an array is created to store lock values associated with particular shared data memory locations. A processor seeking access to a shared data memory location performs atomic swaps of the lock value to the lock array to determine access to a shared data memory location.
摘要翻译： 一种在具有原子交换能力的多处理系统中同步对共享数据的访问的方法。 定义了一个区别的锁定值。 希望访问共享数据存储器位置的处理器执行锁定值到共享数据存储器位置的原子交换。 如果从原子交换接收的数据等同于锁值，则处理器知道存储器位置已被另一个处理器锁定。 然后处理器以间隔重复原子交换，直到收到不等于锁定值的数据。 处理器对数据进行操作，然后对共享数据存储器位置进行写入，以用更新的数据替换锁定值。 在替代实施例中，在不能定义唯一锁定值的情况下，创建阵列以存储与特定共享数据存储器位置相关联的锁定值。 寻求访问共享数据存储器位置的处理器对锁定数组执行锁定值的原子交换以确定对共享数据存储器位置的访问。
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公开(公告)号：US5526487A
公开(公告)日：1996-06-11
申请号：US308401
申请日：1989-02-09
申请人： Alan J. Schiffleger
发明人： Alan J. Schiffleger
IPC分类号： G06F15/173 , G06F15/163
CPC分类号： G06F15/17381
摘要： A system for interprocessor communication including a shared register resource accessible by any one of the processors through the using internal communication paths. The shared register resource is distributed among the processors with each processor including a portion of the total system resource. Each processor includes an access circuit for receiving instructions from the CPU and generating control bytes to be distributed to the shared register resource circuits in each of the processors, which use the control byte to control shared resource access. Each shared register resource circuit is capable of controlling the I/O channels associated with its respective processor. A local access circuit for each CPU is capable of obtaining access to and controlling any of the I/O channels in the system via the shared register resource circuits.
摘要翻译： 一种用于处理器间通信的系统，包括可由任何一个处理器通过使用内部通信路径访问的共享寄存器资源。 共享寄存器资源分布在处理器之间，每个处理器包括总系统资源的一部分。 每个处理器包括用于接收来自CPU的指令的访问电路，并产生要分配给每个处理器中的共享寄存器资源电路的控制字节，其使用控制字节来控制共享资源访问。 每个共享寄存器资源电路能够控制与其相应处理器相关联的I / O通道。 每个CPU的本地访问电路能够通过共享寄存器资源电路获得对系统中的任何I / O通道的访问和控制。
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公开(公告)号：US5499356A
公开(公告)日：1996-03-12
申请号：US173923
申请日：1993-12-28
IPC分类号： G06F9/30 , G06F9/312 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F9/46 , G06F11/36 , G06F15/173 , G06F15/78 , G06F15/80 , G06F12/14
CPC分类号： G06F15/8076 , G06F15/17381 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30069 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3012 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3824 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/526 , G06F2209/521
摘要： A method and apparatus for providing a resource lockout mechanism in a shared memory, multiprocessor system that is capable of performing both a read and write operation during the same memory operation. The load and flag instruction of the present invention can execute a read operation, followed by a write operation of a preselected flag value to the same memory location during the same memory operation. The load and flag instruction is particularly useful as a resource lockout mechanism for use in Monte Carlo applications.
摘要翻译： 一种用于在共享存储器中提供资源锁定机制的方法和装置，该多处理器系统能够在同一存储器操作期间同时执行读取和写入操作。 本发明的加载和标志指令可以在相同的存储器操作期间执行读取操作，随后将预选标志值写入同一个存储器位置。 加载和标志指令特别适用于在蒙特卡罗应用程序中使用的资源锁定机制。
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公开(公告)号：US5487074A
公开(公告)日：1996-01-23
申请号：US406571
申请日：1995-03-20
申请人： Patrick Sullivan
发明人： Patrick Sullivan
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/31858
摘要： An method and apparatus for testing the frequency characteristics of electrical connections between integrated circuits. The apparatus includes circuitry for transmitting a series of signals via the connection from one integrated circuit to another. Each signal of the series is transmitted at a different frequencies. The apparatus further includes circuitry for receiving the series of signals and generating an error signal for each frequency. The method includes sending the series of pre-determined signals from one integrated circuit to another and receiving the series of signals. The method further including the evaluation of the series of signals and the generation of error signals corresponding to each frequency.
摘要翻译： 一种用于测试集成电路之间电气连接频率特性的方法和装置。 该装置包括用于经由连接从一个集成电路向另一个集成电路发送一系列信号的电路。 该系列的每个信号以不同的频率发送。 该装置还包括用于接收一系列信号并为每个频率产生误差信号的电路。 该方法包括将一系列预定信号从一个集成电路发送到另一个并接收一系列信号。 该方法还包括评估一系列信号和产生对应于每个频率的误差信号。
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公开(公告)号：US5481746A
公开(公告)日：1996-01-02
申请号：US218997
申请日：1994-03-29
CPC分类号： G06F9/30032 , G06F15/8076 , G06F15/8084 , G06F9/30036
摘要： Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.
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97.发明授权
公开(公告)号：US5438673A
公开(公告)日：1995-08-01
申请号：US113724
申请日：1993-08-27
申请人： Thomas L. Court , Lawrence T. Hsu , Alan Rivers
发明人： Thomas L. Court , Lawrence T. Hsu , Alan Rivers
CPC分类号： G06F17/5022 , G06F11/22 , G06F11/261
摘要： A method for performing diagnostics on a CPU logic simulator executes certain portions of the diagnostics on a real-machine, and other portions in the software simulator. Those portions that must be executed in the simulator are executed on the simulator, while those portions that need not be executed on the simulator are preferably executed on the real-machine. The method coordinates the execution of the diagnostic functions between the real- machine and the simulator to achieve improved speed of diagnostic execution.
摘要翻译： 用于在CPU逻辑模拟器上执行诊断的方法在实际机器以及软件模拟器中的其他部分执行诊断的某些部分。 必须在模拟器中执行的那些部分在模拟器上执行，而在模拟器上不需要执行的那些部分优选地在实机上执行。 该方法协调实体和仿真器之间诊断功能的执行，以提高诊断执行速度。
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公开(公告)号：US5424658A
公开(公告)日：1995-06-13
申请号：US165156
申请日：1993-12-10
IPC分类号： H03K19/018 , H03K19/0185
CPC分类号： H03K19/01812
摘要： A level shifting circuit which can be implemented as part of a bipolar ECL integrated circuit, provides reliable switching and level shifted output suitable for driving a low voltage CMOS integrated circuit. The circuit includes a level shifting circuit which is connected to trigger a high gain positive feedback bootstrap circuit to reliably ensure switching even under poor signal conditions. An output taken from one of the switched pair is allowed to go to V.sub.CC, 0 volts, or is clamped by a clamping circuit to -3.3 volts, representing the two output states suitable for driving inverted rail CMOS circuitry.
摘要翻译： 可以实现为双极ECL集成电路的一部分的电平移动电路提供适用于驱动低电压CMOS集成电路的可靠的开关和电平移位输出。 电路包括电平移位电路，其连接以触发高增益正反馈自举电路，以可靠地确保即使在差的信号条件下也能切换。 从一个开关对中取出的输出允许转到VCC，0伏，或被钳位电路钳位到-3.3伏特，代表适合于驱动反向轨道CMOS电路的两个输出状态。
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99.发明授权PCB tooling apparatus and method for forming patterns in registration on both sides of a substrate 失效印刷电路板加工装置和方法，用于在衬底的两侧上对准形成图案
公开(公告)号：US5403684A
公开(公告)日：1995-04-04
申请号：US104794
申请日：1993-08-11
CPC分类号： G03F9/00 , H05K3/0082 , H05K2203/1572 , H05K2203/167 , H05K3/0008 , Y10S428/901
摘要： The present invention includes a tooling apparatus designed to provide accurately aligned printed circuits on both major sides of a printed circuit board layer, especially advantageous for use in multi-layer PCB's. Also disclosed is the method manufacture of the apparatus and the methods of using the apparatus. The apparatus includes patterns formed on glass masks attached to frames incorporating alignment pins and slots. The patterns include registration marks for alignment during manufacture of the apparatus. During use, the apparatus allows accurate alignment of patterns on both sides of a PCB layer. Also disclosed is the apparatus with buttons used to pattern PCB layers having pre-drilled Z-axis holes.
摘要翻译： 本发明包括一种设计用于在印刷电路板层的两个主要侧面上提供精确对准的印刷电路的加工设备，特别适用于多层PCB。 还公开了该装置的方法制造和使用该装置的方法。 该装置包括形成在附接到包括对准销和槽的框架的玻璃面罩上的图案。 这些图案包括在制造装置期间对准的对准标记。 在使用期间，该设备允许在PCB层的两侧上精确对准图案。 还公开了具有用于对具有预钻Z轴孔的PCB层进行图案化的装置。
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公开(公告)号：US5355397A
公开(公告)日：1994-10-11
申请号：US950628
申请日：1992-09-24
申请人： David A. Hanson , Edward C. Priest
发明人： David A. Hanson , Edward C. Priest
IPC分类号： G06F1/10 , H03K5/13 , H03K17/296 , H03K17/22 , H03K17/28
摘要： Utilization circuits, such as logic chip circuits, are prevented from receiving the initial one or more pulses of a train of clock pulses produced after the master system clock is started, while the pulses of that train occurring thereafter are coupled to the utilization circuit. This prevents the skew usually present between the initial pulses of the train relative to the subsequent train pulses from adversely effecting operation of the utilization circuits. This clock swallowing preferably blocks a certain predetermined number of initial clock pulses from reaching the rest of the circuitry, although the system is adaptable to allow preselection of the number of such swallowed pulses.
摘要翻译： 诸如逻辑芯片电路之类的利用电路被阻止接收在主系统时钟启动之后产生的一串时钟脉冲的初始一个或多个脉冲，而此后发生的该列的脉冲被耦合到利用电路。 这防止了相对于随后的列车脉冲在列车的初始脉冲之间通常存在的偏斜不利地影响利用电路的操作。 尽管该系统可适应于允许预选这些吞咽脉冲的数目，吞咽这个时钟优选地阻止某些预定数量的初始时钟脉冲到达电路的其余部分。
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