公开(公告)号：US20050237439A1

公开(公告)日：2005-10-27

申请号：US10830206

申请日：2004-04-21

Applicant: Che-Kuei Mai

Inventor： Che-Kuei Mai

IPC: G02F1/133 ,  G02F1/1335 ,  G06F1/18 ,  G06F3/045

CPC classification number: G06F1/182 ,  G02F1/13338 ,  G06F3/045

Abstract: A touch panel. A top transparent substrate includes a top conductive film on its lower surface. A bottom transparent substrate includes a bottom conductive film on its upper surface. An insulating spacer is located between the two conductive films to separate the top conductive film and the bottom conductive film. A plurality of sensing lines, are each disposed on an edge of the top or bottom conductive film and separated from other conductive films or other sensing lines by an adhesive. At least one grounding loop isolated from the top and bottom conductive films by an insulating region, wherein the grounding loop is electrically coupled to an external ground terminal.

Abstract translation: 触摸屏。 顶部透明衬底在其下表面上包括顶部导电膜。 底部透明基板在其上表面上包括底部导电膜。 绝缘间隔物位于两个导电膜之间，以分离顶部导电膜和底部导电膜。 多个感测线路分别设置在顶部或底部导电膜的边缘上，并通过粘合剂与其它导电膜或其它感测线路分离。 至少一个接地环路，通过绝缘区域与顶部和底部导电膜隔离，其中接地环电耦合到外部接地端子。

公开(公告)号：US20050233224A1

公开(公告)日：2005-10-20

申请号：US10941720

申请日：2004-09-15

Applicant: Chang-Ho Tseng ,  Shih-Chang Chang ,  Yaw-Ming Tsai ,  Yu-Ting Hung ,  Ryan Lee

Inventor： Chang-Ho Tseng ,  Shih-Chang Chang ,  Yaw-Ming Tsai ,  Yu-Ting Hung ,  Ryan Lee

IPC: G02B5/08 ,  G02B7/182 ,  G03B21/56 ,  G03F1/14 ,  G03F9/00 ,  G21K5/10 ,  H01J37/08 ,  H01L21/20 ,  H01L21/77 ,  H01L21/84 ,  H01L29/04 ,  H01L29/10 ,  H01L29/786 ,  H01L31/036

CPC classification number: H01L21/0268 ,  H01L21/02686 ,  H01L21/02691 ,  H01L21/2026 ,  H01L27/1214 ,  H01L27/1285 ,  H01L29/78672

Abstract: A method of improving a polysilicon film crystallinity in a sequential lateral solidification process is provided. A mask having a main pattern portion and a compensating pattern portion is provided. The main pattern portion defines a laser beam pattern scanning and transforming an amorphous silicon film into a polysilicon film. The compensating pattern portion adjacent to the main pattern portion adjusts the energy of the laser beam injected to the polysilicon film to improve the grain shape thereof.

Abstract translation: 提供了一种在顺序侧向凝固过程中改善多晶硅膜结晶度的方法。 提供具有主图案部分和补偿图案部分的掩模。 主图案部分限定了激光束图案扫描并将非晶硅膜转变成多晶硅膜。 与主图案部分相邻的补偿图案部分调节注入多晶硅膜的激光束的能量，以改善其晶粒形状。

公开(公告)号：US20050231487A1

公开(公告)日：2005-10-20

申请号：US11041220

申请日：2005-01-25

Applicant: Jheng Ming

Inventor： Jheng Ming

IPC: G09G3/36

CPC classification number: G02F1/13338

Abstract: A driving circuit of a touch panel is formed by the photolithographic process on the liquid crystal display (LCD) panel to reduce the area of the driving circuit. The method includes providing an LCD panel having a common substrate; and forming a touch panel on the common substrate. First, a first conducting layer is formed on the common substrate, and then a second patterned conducting layer is formed on the first conducting layer and on a peripheral region of the LCD panel by a photolithographic process. The common substrate of the LCD panel is used as an upper substrate of the LCD panel and as a lower substrate for the touch panel.

Abstract translation: 通过在液晶显示器（LCD）面板上的光刻工艺形成触摸面板的驱动电路，以减小驱动电路的面积。 该方法包括提供具有公共衬底的LCD面板; 以及在公共基板上形成触摸面板。 首先，在公共衬底上形成第一导电层，然后通过光刻工艺在第一导电层上和LCD面板的周边区域上形成第二图案化导电层。 LCD面板的公共基板用作LCD面板的上基板和用作触摸面板的下基板。

公开(公告)号：US20050225251A1

公开(公告)日：2005-10-13

申请号：US10998404

申请日：2004-11-29

Applicant: Wei-Chieh Hsueh

Inventor： Wei-Chieh Hsueh

IPC: G09G3/10 ,  G09G3/32

CPC classification number: G09G3/3241 ,  G09G2300/0814 ,  G09G2310/0262

Abstract: A pixel structure and its driving method, which are used in the active matrix organic illuminated displays, are described. The pixel structure has four transistors, a capacitor and three signal lines. The first and second transistors are used as the switching transistors and controlled by the first and second scan lines, respectively. The third and fourth transistors together constitute a current mirror to equalize the current flows through the OLED in each pixel and the writing in current in the data line. Therefore, the illumination of the OLED between each pixel will be more uniform and is not influenced by the threshold voltage.

Abstract translation: 描述了用于有源矩阵有机照明显示器中的像素结构及其驱动方法。 像素结构具有四个晶体管，一个电容器和三个信号线。 第一和第二晶体管分别用作开关晶体管并由第一和第二扫描线控制。 第三和第四晶体管一起构成电流镜以均衡在每个像素中通过OLED的电流和在数据线中的电流写入。 因此，每个像素之间的OLED的照明将更加均匀，并且不受阈值电压的影响。

公开(公告)号：US20050224793A1

公开(公告)日：2005-10-13

申请号：US10954674

申请日：2004-09-30

Applicant: Shih-Chang Chang ,  Yaw-Ming Tsai

Inventor： Shih-Chang Chang ,  Yaw-Ming Tsai

IPC: H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L31/036

CPC classification number: H01L27/1237 ,  H01L27/1214

Abstract: To satisfy the different requirement of TFTs function as peripheral driving circuit and pixel switching device, the modified TFT structure with various thicknesses of gate insulating layers is disclosed. For the peripheral driving circuit, the thinner thickness of the gate-insulating layer is formed, the higher driving ability the TFT performs. However, for the pixel switching device, the thicker thickness of the gate insulating layer is formed, the better reliability the TFT has. The present invention provides a first TFT (peripheral driving circuit) comprising a first gate insulating layer and a second TFT (pixel switching device) comprising a first and second gate insulating layer. Thus, the gate insulating layer of the peripheral driving circuit has a thickness less then that of the pixel switching device.

Abstract translation: 为了满足作为外围驱动电路和像素开关器件的TFT的不同要求，公开了具有各种厚度的栅极绝缘层的改进的TFT结构。 对于外围驱动电路，形成栅极绝缘层的厚度越薄，TFT的驱动能力越强。 然而，对于像素开关器件，形成栅极绝缘层的较厚的厚度，TFT具有更好的可靠性。 本发明提供一种第一TFT（外围驱动电路），包括第一栅极绝缘层和包括第一和第二栅极绝缘层的第二TFT（像素开关器件）。 因此，外围驱动电路的栅极绝缘层的厚度小于像素开关器件的厚度。

公开(公告)号：US06951793B2

公开(公告)日：2005-10-04

申请号：US10855542

申请日：2004-05-27

Applicant: An Shih

Inventor： An Shih

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/786

CPC classification number: H01L29/66757 ,  H01L29/78621

Abstract: A low-temperature polysilicon thin film transistor having a buried LDD structure is provided. Two heavily doped regions are formed in a semiconductor layer and distributed just below a surface of the semiconductor layer. Two LDD regions are both sandwiched between the two heavily doped regions in a direction substantially parallel to the surface of semiconductor layer, and separated from the surface of the semiconductor layer by a portion of the semiconductor layer. The process for producing such a thin film transistor is also provided. A first, a second and a third doping materials are injected into a semiconductor layer in different directions to form heavily doped regions and LDD regions.

Abstract translation: 提供具有埋入LDD结构的低温多晶硅薄膜晶体管。 在半导体层中形成两个重掺杂区域，并分布在半导体层的表面正下方。 两个LDD区域在基本上平行于半导体层的表面的方向上夹在两个重掺杂区域之间，并且通过半导体层的一部分与半导体层的表面分离。 还提供了制造这种薄膜晶体管的工艺。 将第一，第二和第三掺杂材料注入不同方向的半导体层中以形成重掺杂区域和LDD区域。

公开(公告)号：US20050186715A1

公开(公告)日：2005-08-25

申请号：US11040747

申请日：2005-01-24

Applicant: Jr-Hong Chen ,  Gwo-Long Lin ,  Chih-Fang Chen

Inventor： Jr-Hong Chen ,  Gwo-Long Lin ,  Chih-Fang Chen

IPC: G02F1/1368 ,  G02F1/1362 ,  G09F9/30 ,  H01L21/00 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/77 ,  H01L21/82 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/0248 ,  G02F1/136204 ,  H01L27/1214

Abstract: A method of fabricating an array of structures sensitive to ESD is disclosed. First, an array of structures is provided on a substrate, with the structures conductively coupled by interconnections. Thereafter, the interconnections are removed before fabricating another array of structures. Therefore, the structures have equal potential. Further, an electrostatic discharge structure is provided near the periphery of the substrates.

Abstract translation: 公开了一种制造对ESD敏感的结构阵列的方法。 首先，在衬底上提供一组结构，其结构通过互连导电耦合。 此后，在制造另一个结构阵列之前去除互连。 因此，结构具有相同的潜力。 此外，在基板的周边附近设置静电放电结构。

公开(公告)号：US06933993B2

公开(公告)日：2005-08-23

申请号：US10438987

申请日：2003-05-16

Applicant: Huo-Long Peng ,  Chaung-Ming Chiu ,  Kuang-Lung Kuo ,  Jing-Yi Chang ,  Tzu-Seng Yang

Inventor： Huo-Long Peng ,  Chaung-Ming Chiu ,  Kuang-Lung Kuo ,  Jing-Yi Chang ,  Tzu-Seng Yang

IPC: G02F1/1333 ,  G02F1/1335 ,  G02F1/1343

CPC classification number: G02F1/133512 ,  G02F1/133514 ,  G02F2001/133388

Abstract: The present invention provides a color liquid crystal display device in which a color filter layer is formed on an array substrate. The array substrate includes a scan line and a data line forming a pixel, on which a thin film transistor is formed, and a pixel electrode is connected to the thin film transistor. A black matrix layer is formed on the array substrate. A black matrix frame is formed around the periphery of the black matrix layer. A color filter layer is formed on the array substrate and the black matrix layer, and extends to cover the black matrix frame.

Abstract translation: 本发明提供了一种在阵列基板上形成滤色器层的彩色液晶显示装置。 阵列基板包括扫描线和形成像素的数据线，在其上形成薄膜晶体管，并且像素电极连接到薄膜晶体管。 在阵列基板上形成黑矩阵层。 在黑矩阵层的周围形成黑矩阵框。 在阵列基板和黑矩阵层上形成滤色器层，并延伸以覆盖黑矩阵框架。

公开(公告)号：US20050168673A1

公开(公告)日：2005-08-04

申请号：US10964031

申请日：2004-10-12

Applicant: Li-Sen Chuang ,  Wei-Chih Chang ,  Chia-Yi Tsai ,  Chi-Jain Wen

Inventor： Li-Sen Chuang ,  Wei-Chih Chang ,  Chia-Yi Tsai ,  Chi-Jain Wen

IPC: G02F1/133 ,  G02F1/1335 ,  G02F1/1343

CPC classification number: G02F1/133555 ,  G02F2201/52

Abstract: A transflective liquid crystal display has a plurality of pixel electrode layers corresponding to a plurality of color elements. A first pixel electrode layer has a first reflective region and a first transmissive region. A second pixel electrode layer has a second reflective region and a second transmissive region. A third pixel electrode layer has a third reflective region and a third transmissive region. The first reflective region is larger than the second reflective region, and the first reflective region is larger than the third reflective region.

Abstract translation: 半透射型液晶显示器具有对应于多个色素的多个像素电极层。 第一像素电极层具有第一反射区域和第一透射区域。 第二像素电极层具有第二反射区和第二透射区。 第三像素电极层具有第三反射区域和第三透射区域。 第一反射区域大于第二反射区域，第一反射区域大于第三反射区域。

公开(公告)号：US06922095B2

公开(公告)日：2005-07-26

申请号：US10692098

申请日：2003-10-23

Applicant: Chaung-Ming Chiu

Inventor： Chaung-Ming Chiu

IPC: H01L31/0328 ,  H03K19/0185 ,  H03L5/00 ,  H03L7/081

CPC classification number: H03K19/01855 ,  G09G2310/0289

Abstract: A voltage level shifter includes a front stage circuit periodically generating a first control signal and a second control signal in response to a first input clock signal and a second input clock signal complementary to the first input clock signal; a switch circuit including two PMOS transistors connected between a maximum voltage and a minimum voltage in series, wherein a third control signal is outputted from a conjunction of the two PMOS transistors, and the first and second control signals are coupled to the gate electrodes of the two PMOS transistors, respectively; and a driving circuit receiving the third control signal and outputting an output clock signal having a peak-to-peak value larger than a peak-to-peak value of the input clock signal. The voltage level shifter is implemented by essentially PMOS transistors.

Abstract translation: 电压电平移位器包括响应于与第一输入时钟信号互补的第一输入时钟信号和第二输入时钟信号周期性地产生第一控制信号和第二控制信号的前级电路; 包括连接在最大电压和最小电压串联的两个PMOS晶体管的开关电路，其中从两个PMOS晶体管的结合输出第三控制信号，并且第一和第二控制信号耦合到 两个PMOS晶体管; 以及驱动电路，接收第三控制信号并输出​​具有大于输入时钟信号的峰 - 峰值的峰峰值的输出时钟信号。 电压电平移位器基本上由PMOS晶体管实现。